This paper presents a switched-capacitor-based integer compute unit in 5nm CMOS that is designed as a drop-in replacement for an equivalent digital unit to improve power efficiency by 2. 5X. Integer multiply-accumulate (MAC) operations are recast as a scaled sum of l-b MACs, where each l-b MAC is performed using a population counter (PPCTR) circuit. Each PPCTR is an enhanced SAR ADC that performs l-b multiplication, D-A conversion, accumulation, and A-D conversion with no loss of precision. The compute unit has 4864 PPCTRs arranged as 64 processing engines, with a total throughput of 104.9 TOPS and 650 TOPS/W power efficiency for l-b MACs.

We report a new approach to building an ASIC-style superconducting SFQ logic cell library for the 8-layer 0.35 μm Niobium SFQ5ee process from MIT LL. The developed library layout template supports XY routing with Passive Transmission Lines (PTLs) and targets conventional Place-and-Route assembly for the design of VLSI Random Logic Macros (RLMs). The designed library gates are based on clockless Dynamic SFQ (DSFQ) logic which allows one to directly implement deep combinational logic clouds. The full library gates communicate only via an XY PTL routing plane, while internally they are assembled from smaller self-contained subgates, connected via inductors and placed in one template row. We report test results for two chips that independently verify library subgate assemblies that are used to build DSFQ logic gates as well as active PTL interconnect; on-chip testbenches provide low-speed and high-speed (GHz) test modes. We have achieved low-speed and high-speed functionality of both the DSFQ logic gates (AND, OR, and AO21) and active interconnect circuitry (transmitters Tx and receivers Rx) used for communicating SFQ signals over 700 μm PTLs and short (∼50 μm) series inductor-resistor (LR) connections. The measured speed of the OR and AND logic circuits exceeded 10 GHz, while the speed for PTLs and LR connections was more than 10 and 30 GHz, respectively.

A 56 GS/s 8-bit asynchronous SAR ADC fabricated in 4nm CMOS technology is demonstrated. The 16x4 interleaved ADC uses a novel bootstrapping technique and a class-AB follower in the 1 st rank interleaver. It achieves a broad input common-mode (CM) range; from 0.3V to 0.6V, the total harmonic distortion stays below -52dB at 4.1 GHz with -0.2dBFS amplitude at 0.8V PPD maximum full scale. The ADC includes analog foreground calibration means for offset, gain, skew, and bandwidth. The measured ENOB is 6.5 at low frequency and stays above 5.2 up to Nyquist frequency. The bandwidth is higher than 27 GHz. The ADC uses a single 0.8V supply voltage and achieves an efficiency of 47 fJ/conv.step.

We have introduced a new class of dc-powered Single Flux Quantum (SFQ) logic that uses dynamic (self-resetting) internal states to achieve completely clock-free gate operation and provide high immunity to input data skew. We call it DSFQ (dynamic SFQ) logic. We have successfully designed and tested a 2-input DSFQ AND gate and showed its ability to hold dynamically its internal states for over 25 ps while operating at 10 GHz clock frequency. We also demonstrated picosecond-scale dynamics of DSFQ circuit with an on-chip Josephson sampler, with only low-speed interfaces required.

This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is -11.7 dBm OMA at a bit error rate of 10(-12) with PRBS31 data, providing 12.9-dB link margin.

An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.

As CMOS devices continue to scale down in voltage and area, digital-based high-speed serial I/Os [1] become increasingly competitive with analog-based designs [2,3]. In addition to offering the PVT-independent performance of digital functions and superior power and area scaling to future technology nodes, digital-based I/Os can support advanced line modulation techniques that will become necessary as long-reach electrical channel data rates scale to 56Gb/s and beyond. The key enablers of a digital receiver are power and area efficient analog to digital conversion (ADC) and digital channel equalization. This paper describes the design of a 25Gb/s 2-level digital serial line receiver including a ¼-rate 5b flash ADC, an 8-tap feed-forward equalizer (FFE), an 8-tap decision-feedback equalizer (DFE), and a baud-rate clock and data recovery circuit (CDR). The receiver features a flash ADC, which employs a new power and area efficient slicer design capable of achieving high-precision (∼1mV) threshold accuracy with an associated on-chip calibration system. The 32nm SOI CMOS receiver achieves error-free operation with margin on a reflective transmission-line channel with 40dB half-baud loss.

Rapidly reconfigurable optical networks that keep the data in the optical domain potentially offer significant advantages in latency, bandwidth and power dissipation. Existing optical switch technologies (e.g., MEMS-based) are limited to millisecond-scale reconfiguration times, severely reducing their application space. The emerging field of silicon photonics enables optical switches operating on a nanosecond scale [1]. However, full utilization of the speed of these switches requires nanosecond-scale burst-mode transceivers, similar to those used in passive optical networks [2]. In this work, we reporta burst-mode receiver for optical links in a dynamically reconfigurable network. Through the introduction of interlocking search algorithms, a robust 25Gb/s burst-mode operation is achieved with 31ns lock time, -10.9dBm sensitivity, and 4.4pJ/b efficiency.

A DC-coupled burst-mode receiver performs optical power calibration in 12.5ns, achieves phase lock in 18.5ns and tracks input data using a CDR. The sensitivity of the 4.4pJ/bit receiver is -10.9dBm (BER <; 10-12) at 25Gb/s.

A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

A power-scalable 2-Byte I/O operating at 12-Gb/s per lane is reported. The I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels. Measurements of a test chip fabricated in 32nm SOI CMOS technology demonstrate 1.4-pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9-pJ/b efficiency over 20” Megtron-6 PCB traces.