Recent work in structure–processing relationships of polymer semiconductors have demonstrated the versatility and control of thin-film microstructure offered by meniscusguided coating (MGC) techniques. Here, we analyze the qualitative and quantitative aspects of solution shearing, a model MGC method, using coating blades augmented with arrays ofpillars. The pillars induce local regions of high strain rates—both shear and extensional—not otherwise possible with unmodified blades, and we use fluid mechanical simulations to modeland study a variety of pillar spacings and densities. We then perform a statistical analysis of 130 simulation variables to find correlations with three dependent variables of interest: thin-filmdegree of crystallinity and transistor field-effect mobilities for charge-transport parallel (Μpara) and perpendicular (Μperp) to the coating direction. Our study suggests that simple fluid mechanicalmodels can reproduce substantive correlations between the induced fluid flow and important performance metrics, providing a methodology for optimizing blade design. Polymer semiconductors have opened up a new frontier of electronics that can be flexible, stretchable, implantable, or biodegradable. While the chemical and electronic properties of these materials are important for their function as the active material in organic electronic devices, the manner by which these organic semiconductors are deposited onto a substrate can significantly influence its charge-transport properties. While a variety of techniques have been investigated to enhance charge-transport behavior, there are few reports approaching the issue in terms of the fluid dynamical considerations relevant during deposition from the solution phase. In this article, we analyze the fluid flow that occurs during thin-film deposition by solution shearing, a representative meniscusguided coating method amenable to high-throughput processing. We investigate a variety of variables related to fluid flow that can be estimated from fluid mechanical simulations of solution shearing with a coating blade patterned with a regular array of pillars used to induce higher fluid strain rates. We find correlations suggestive of underlying relationships between strain rates associated with certain directions and polymer charge-transport properties in the final deposited film. This article establishes a statistical approach using simulation data that can guide patterned blade design to enhance polymer deposition and realize high-performance devices.

Crucial to the development and refinement of organic electronics is a fundamental understanding of how deposition processes affect the active material’s resulting microstructure in the thin film. Meniscus-guided coating (MGC) methods are attractive because of their amenability to high-throughput, industrially relevant continuous processes like roll-to-roll deposition, but the mechanism of solid film formation has not been elucidated and is valuable for the precise control of thin-film morphology and thus ultimate device performance. In this work, we investigate the microstructural evolution of thin films of a diketopyrrolopyrrole–terthiophene donor–acceptor polymer semiconductor using both in situ and ex situ X-ray diffraction methods. On the basis of a comparison of disorder between the film bulk and the top surface and a depth profiling of the out-of-plane orientation of crystallites, we find that faster coating speeds introduce more disorder into the resulting films because the stochastic nucleation of...

Targeting flexible display backplanes and circuitry, BASF is developing high performance materials for Organic Field-Effect Transistors. Here we present our recent development focusing on directly photo-patternable semiconductors and dielectrics, as well as new semiconductors for solution-processed transistors with mobilities of up to 4 cm2/Vs.

Rational use of novel high-performance semiconductors in field-effect transistors (FETs) requires exact knowledge of the dominating charge transport mechanisms. In particular, the distinction between contact- and semiconductor-limited transport is important in FETs with small channel lengths. Here, we analyze the relative contributions of contact limitation and intrinsic conductivity of FETs based on mechanically exfoliated multilayers of the high performance n-type semiconductor molybdenum disulfide (MoS2). Based on a lithography-free fabrication process, we realize FETs with room temperature mobility (mu) of up to 46.8 cm2/Vs and ION/IOFF ratio of up to 105. Using temperature- and bias-dependent charge transport measurements, we are able to show that the intrinsic bulk transport in the flake can be best described by a phonon-limited band transport model with a conductive bulk at room temperature that freezes out upon cooling of the sample. In addition, we notice an increase of mu by a factor of 25 when using a self-assembled monolayer (SAM)-modified SiO2/MoS2 interface. More importantly, we show that the choice of drainsource bias (VDS) is crucial when interpreting MoS2 transport measurements, while for large VDS the intrinsic semiconductor transport properties can be observed, a strong contact limitation appears at low VDS. Our combined measurements allow us to distinguish between the effect of bulk and semiconductor/dielectric interface transport and the effect of contact resistance on the electrical transport properties. (C) 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

A method for the formation of a low-temperature hybrid gate dielectric for high-performance, top-gate ZnO nanowire transistors is reported. The hybrid gate dielectric consists of a self-assembled monolayer (SAM) and an aluminum oxide layer. The thin aluminum oxide layer forms naturally and spontaneously when the aluminum gate electrode is deposited by thermal evaporation onto the SAM-covered ZnO nanowire, and its formation is facilitated by the poor surface wetting of the aluminum on the hydrophobic SAM. The hybrid gate dielectric shows excellent electrical insulation and can sustain voltages up to 6 V. ZnO nanowire transistors utilizing the hybrid gate dielectric feature a large transconductance of 50 μS and large on-state currents of up to 200 μA at gate-source voltages of 3 V. The large on-state current is sufficient to drive organic light-emitting diodes with an active area of 6.7 mm(2) to a brightness of 445 cd/m(2). Inverters based on ZnO nanowire transistors and thin-film carbon load resistors operate with frequencies up to 30 MHz.

In the late 1960s, a new concept was proposed for an infrared absorbing device called a “rectenna” that, combining an antenna and a nanoscale metal-insulator-metal diode rectifier, collects electromagnetic radiation in the terahertz regime, with applications as detectors and energy harvesters. Previous theories hold that the diode rectifies the induced terahertz currents. Our results, however, demonstrate that the Seebeck thermal effect is the actual dominant rectifying mechanism. This new realization that the underlying mechanism is thermal-based, rather than tunneling-based, can open the way to important new developments in the field, since the fabrication process of rectennas based on the Seebeck effect is far simpler than existing processes that require delicate tunnel junctions. We demonstrate for the first time the fabrication of a rectenna array using an efficient parallel transfer printing process featuring nearly one million elements.

Nanoscale metal-insulator-metal (MIM) diodes represent important devices in the fields of electronic circuits, detectors, communication, and energy, as their cutoff frequencies may extend into the "gap" between the electronic microwave range and the optical long-wave infrared regime. In this paper, we present a nanotransfer printing method, which allows the efficient and simultaneous fabrication of large-scale arrays of MIM nanodiode stacks, thus offering the possibility of low-cost mass production. In previous work, we have demonstrated the successful transfer and electrical characterization of macroscopic structures. Here, we demonstrate for the first time the fabrication of several millions of nanoscale diodes with a single transfer-printing step using a temperature-enhanced process. The electrical characterization of individual MIM nanodiodes was performed using a conductive atomic force microscope (AFM) setup. Our analysis shows that the tunneling current is the dominant conduction mechanism, and the electrical measurement data agree well with experimental data on previously fabricated microscale diodes and numerical simulations.

Nano diodes show great potential for applications in detectors, communications and energy harvesting. However, to make them suitable for low-cost mass production, these nano devices have to be fabricated reliably over large areas while minimizing process time and costs. Printing techniques are promising candidates to overcome these economical drawbacks of conventional nanolithography without a significant loss in structure quality. In this work, we focus on nano transfer printing (nTP) to fabricate nm-scale diodes over extensive areas. Using a temperature-enhanced process, several millions of diodes were transfer-printed in one single step. We show the reliable transfer of functioning Schottky and MIM diodes of different sizes, which demonstrates the versatility and usability of our approach (nTP), paving the way to numerous applications in the fields of e.g. infrared detection or energy harvesting. The nano devices are characterized electrically by conductive Atomic Force Microscopy (c-AFM) measurements. For these MIM structures, quantum-mechanical tunneling was determined to be the main conduction mechanism across the metal-oxide-metal junction.

A novel approach for the fabrication of transistors and circuits based on individual single-crystalline ZnO nanowires synthesized by a low-temperature hydrothermal method is reported. The gate dielectric of these transistors is a self-assembled monolayer that has a thickness of 2 nm and efficiently isolates the ZnO nanowire from the top-gate electrodes. Inverters fabricated on a single ZnO nanowire operate with frequencies up to 1 MHz. Compared with metal-semiconductor field-effect transistors, in which the isolation of the gate electrode from the carrier channel relies solely on the depletion layer in the semiconductor, the self-assembled monolayer dielectric leads to a reduction of the gate current by more than 3 orders of magnitude.

Bottom-gate, top-contact organic thin-film transistors (TFTs) with excellent static characteristics (on/off ratio: 10(7) ; intrinsic mobility: 3 cm(2) (V s)(-1) ) and fast unipolar ring oscillators (signal delay as short as 230 ns per stage) are fabricated. The significant contribution of the transfer length to the relation between channel length, contact length, contact resistance, effective mobility, and cutoff frequency of the TFTs is theoretically and experimentally analyzed.

Organic thin-film transistors based on the vacuum-deposited small-molecule conjugated semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) have been fabricated and characterized. The transistors have field-effect mobilities as large as 2 cm2/V s and an on/off ratio of 108. Owing to the large ionization potential of DNTT, the TFTs show excellent stability for periods of several months of storage in ambient air. Unipolar ring oscillators based on DNTT TFTs with a channel length of 10 μm oscillate with a signal propagation delay as short as 7 μsec per stage at a supply voltage of 5 V. We also show that DNTT TFTs with usefully small channel width/length ratio are able to drive blue organic LEDs to a brightness well above that required for active-matrix displays.

A fabrication process for the monolithic integration of field-effect transistors based on individual carbon nanotubes and load resistors based on vacuum-evaporated carbon films into fast unipolar logic circuits on glass substrates is reported for the first time. The individual-carbon-nanotube transistors operate with relatively small gate-source and drain-source voltages of 1 V and combine large transconductance (up to 6 μS), large ON/OFF ratio (>10(4)), and short switching delay time constants (12 ns). The thin-film carbon load resistors provide linear current-voltage characteristics and resistances between 300 kΩ and 100 MΩ, depending on the layout of the resistors and the thickness of the vacuum-evaporated carbon films. Various combinational circuits (NAND, NOR, AND, OR gates) as well as a sequential circuit ( ̅S ̅R NAND latch) have been fabricated and characterized. Although these unipolar circuits cannot compete with optimized complementary circuits in terms of integration density and static power consumption, they offer the possibility of realizing air-stable, low-voltage integrated circuits with promising static and dynamic performance on unconventional substrates for large-area electronics applications, such as displays or sensors.

To suppress undesirable short-channel effects in organic transistors with nanoscale lateral dimensions, aggressive gate-dielectric scaling (using an ultra-thin monolayer-based gate dielectric) and area-selective contact doping (using a strong organic dopant) are introduced into organic transistors with channel lengths and gate-to-contact overlaps of about 100 nm. These nanoscale organic transistors have off-state drain currents below 1 pA, on/off current ratios near 107, and clean linear and saturation characteristics. Organic thin-film transistors (TFTs) are of interest for electronic applications on flexible plastic substrates, such as rollable or foldable active-matrix displays,1 conformable sensor arrays,2 and flexible identification tags.3 Due to the relatively small intrinsic field-effect mobility in most conjugated organic semiconductors (<5 cm2 V−1 s−1), the maximum frequency at which organic TFTs can be operated is usually limited to about 1 MHz.3 For certain applications, such as the integration of the row and column drivers for high-resolution active-matrix displays or sensor arrays directly on the flexible backplane,4, 5 organic TFTs that can be operated at higher frequencies (>10 MHz) are highly desirable. Such high frequencies are indeed feasible, provided the lateral dimensions of the organic TFTs are sufficiently small (about 100 nm). However, TFTs with such small lateral dimensions will suffer from a variety of detrimental short-channel effects, unless a number of important scaling requirements are observed in the design and fabrication of the transistors. Here we report on the successful fabrication and detailed analysis of organic TFTs with channel lengths and gate overlaps of about 100 nm in which the short-channel effects are greatly suppressed by area-selective contact doping (using a strong organic dopant) and by aggressive gate-dielectric scaling (using a 5.7 nm-thick, low-temperature-processed gate insulator based on a mole­cular self-assembled monolayer). As a result, these nanoscale organic TFTs have off-state drain currents below 1 pA, on/off current ratios near 107, as well as clean linear and saturation characteristics. The transconductance of these transistors reaches 0.4 S m−1, which is the largest transconductance reported for organic TFTs with patterned gate electrodes. The gate electrodes and source/drain contacts of organic TFTs are usually defined by photolithography,1, 3, 4 shadow-masking,2, 5 or inkjet printing,6 and the minimum feature size that can be achieved with these methods is usually above 1 μm. The Cambridge University group has recently developed an innovative self-aligned inkjet-printing process that makes it possible to fabricate organic TFTs with a channel length of less than 200 nm and gate-to-source and gate-to-drain overlaps of less than 700 nm.7, 8 Organic TFTs with such small lateral dimensions can in principle reach frequencies above 10 MHz, despite the modest mobilities in organic semiconductors, and even if the TFTs are operated with low voltages of about 5 V or less (see Supporting Information, SI). The ability to manufacture organic TFTs with nanoscale lateral dimensions using large-area-compatible printing techniques, such as demonstrated by the Cambridge group, creates unique and exciting opportunities for organic TFTs in high-frequency electronic applications. However, when the channel length of a field-effect transistor is reduced, the thickness of its gate dielectric must also be reduced in order to keep the ratio between the channel length and the gate-dielectric thickness large, ideally at least about 20.9 Otherwise the electric potential along the carrier channel will be dominated by the lateral electrical field (determined by the drain–source voltage VDS and the channel length L), rather than by the transverse electric field (determined by the gate–source voltage VGS and the gate-dielectric thickness tdiel), which has undesirable consequences on the transistor characteristics, including large off-state currents, small on/off current ratios, and poor current saturation. This can be seen in most previous reports on organic TFTs with submicrometer lateral dimensions.7-17 A second important requirement for the realization of nanoscale organic TFTs is a substantial reduction of the contact resistance. If the contact resistance is not reduced along with the reduction in channel length, the drain current at small drain–source voltages will be greatly suppressed, which causes the well-documented nonline­arity in the output characteristics of the transistors.6-17 The contact resistance of organic TFTs can in principle be reduced by area-selective impurity doping. If the energy of the lowest unoccupied molecular orbital (LUMO) of the dopant mole­cules is near (ideally below) the energy of the highest occupied molecular orbital (HOMO) of the host semiconductor, electrons can move from the host semiconductor to the dopant molecules, thereby creating excess holes in the semiconductor and thus increasing its electrical conductivity.18-22 This concept has previously been applied to organic p-channel TFTs with channel lengths down to 300 nm.23-28 In all these reports, however, the gate electrode of the TFTs was not patterned. Instead of a patterned gate electrode, a conducting silicon wafer served not only as the substrate, but also as the gate electrode for all the TFTs on the substrate. As a result, the overlap between the gate electrode and the source and drain contacts of the TFTs was very large (>100 μm). Such a large gate overlap has the distinct advantage that the charge injection from the contact into the semiconductor spreads across a large contact area,29, 30 but it has the distinct disadvantage of producing a large parasitic capacitance that limits the maximum frequency at which the transistors can be operated (see SI). Reducing the gate overlaps helps to reduce the parasitic capacitance, but will also create the problem of a severely reduced contact length and hence possibly much larger contact resistance.29, 30 Thus, a key question that has so far not been addressed is how useful the concept of contact doping is for organic TFTs with submicrometer channel length and with submicrometer gate overlap. To answer this question, electron-beam lithography and a proprietary organic dopant (Novaled NDP-9) have been employed in order to fabricate organic TFTs with submicrometer gate electrodes, precisely aligned, chemically doped source/drain contacts, and submicrometer channel length. Electron-beam lithography is obviously incompatible with large-area electronics, but it is helpful in understanding the material requirements for aggressive gate-dielectric scaling and controlled contact doping, until high-resolution printing techniques7, 8 become more routine. The organic TFTs developed here are based on the inverted staggered (bottom-gate, top-contact) device architecture. Each TFT has an aluminum gate electrode that is patterned by electron-beam lithography, a 5.7 nm-thick gate dielectric (composed of a thin AlOx layer created by surface oxidation and an organic self-assembled monolayer grown from solution31), a 20 nm-thick layer of the air-stable organic semiconductor dinaphtho-[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT),32-34 and 25 nm-thick gold source/drain contacts deposited on top of the organic semiconductor layer. To pattern nanoscale source/drain contacts on top of the semiconductor layer without damaging the organic semiconductor by exposure to organic solvents35 or elevated temperatures,36 an elegant process was employed that was developed by the RIKEN group, which uses a suspended resist bridge created by electron-beam lithography prior to the deposition of the organic semiconductor layer.15, 23-25 During the deposition of the organic semiconductor, the substrate is tilted, so that the semiconductor forms a continuous layer underneath the suspended resist bridge, while the deposition of the gold source/drain contacts is performed at an angle of 90°, using the resist bridge as a high-resolution shadow mask. Aside from the resist bake, the maximum process temperature is 60 °C, which is fully compatible with flexible polymeric substrates. The fabrication process is described in detail in the SI. Figure 1 shows a schematic cross-section and three electron microscopy images of the submicrometer organic TFTs. Top-contact organic TFTs with deep-submicrometer channel length and gate overlap and a 5.7 nm-thick low-temperature-processed gate dielectric. a) Schematic cross-section showing the patterned metal gate electrode, the gate dielectric (3.6 nm AlOx + 2.1 nm self-assembled monolayer), the organic semiconductor layer, the Au source/drain contacts, and the suspended resist bridge created by electron-beam lithography. b) Scanning electron microscope image of the suspended resist bridge and the Au source/drain contacts (sample tilted for imaging). c) Cross-sectional transmission electron microscope image of a TFT with a channel length of 100 nm and a gate overlap of 200 nm. The patterned Al gate electrode, the gate dielectric, and the source/drain contacts are clearly distinguished. The 20 nm-thick organic semiconductor layer, sandwiched between the gate dielectric and the source/drain contacts, is not resolved in this image. d) Oxygen map recorded by electron energy loss spectroscopy in a transmission electron microscope. The oxygen signals from the SiO2 (top layer of the substrate) and from the AlOx (part of the gate dielectric) are clearly seen. All electrical measurements were performed in ambient air at room temperature. The electrical characteristics of a TFT with a channel length of 90 nm, a channel width of 500 nm, and a gate overlap of 200 nm are shown in Figure 2. The ratio between the channel length (90 nm) and the gate-dielectric thickness (5.7 nm) is sufficiently large to facilitate strong gate coupling, so the off-state drain current is very small (about 10−13 A) and the on/off current ratio is very large (107), essentially identical to TFTs with a channel length of 30 μm.32 This on/off current ratio is the largest reported for a submicrometer organic TFT. The field-effect mobility extracted from the current–voltage characteristics is 0.05 cm2 V−1 s−1. The TFT has a maximum transconductance of 0.2 μS (also extracted from the current–voltage characteristics) and a gate capacitance of 1.7 fF (calculated from the device geometry and materials parameters), so the maximum frequency of operation predicted by Equation S1, SI, is 20 MHz. The transconductance normalized to the channel width (500 nm) is 0.4 S m−1, which is the largest width-normalized transconductance that has so far been reported for an organic TFT with a patterned gate electrode. (A transconductance of 0.7 S m−1 has recently been obtained for organic TFTs fabricated on a conducting silicon wafer serving both as the substrate and as a global gate electrode.25) Electrical characteristics of a submicrometer TFT without contact doping (L = 90 nm, ΔL = 200 nm). a) Transfer characteristics. The off-state drain current (at VGS = 0 V) and the gate current are near the detection limit (<10−13 A), the on/off current ratio is 107, the subthreshold swing is 160 mV dec−1, and the field-effect mobility extracted from the transfer characteristics is 0.05 cm2 V−1 s−1. The hysteresis in the current–voltage curve is negligible. The molecular structure of the organic semiconductor DNTT is shown in the inset. b) Output characteristics of the same device. For large drain–source voltages (VDS > VGS-Vth) the drain current shows good saturation, despite the small channel length. For small drain–source voltages (VDS < VGS-Vth), the drain current is greatly suppressed due to the large contribution of the contact resistance to the total device resistance. c) Transconductance (gm = ∂ID/∂VGS) per channel width as a function of gate-source voltage for the same device. The width-normalized transconductance reaches a maximum of 0.4 S m−1, which is the largest width-normalized transconductance reported for an organic transistor with a patterned gate electrode. However, due to the large contribution of the contact resistance in these nanoscale TFTs, the output characteristics in Figure 2 show the familiar non-linearity of the drain current at small drain–source voltages (-1 V ≤ VDS ≤ 0 V). In order to reduce the contact resistance and improve the drain-current linearity, we have also fabricated TFTs with a nominally 1 nm thick, vacuum-deposited layer of the organic molecular dopant NDP-9 inserted between the semiconductor layer and the gold source/drain contacts. Atomic force microscope (AFM) images of DNTT layers without NDP-9 and with various amounts of NDP-9 deposited on top of a DNTT layer are shown in SI, Figure S2. The images indicate that depositing a 1 nm thick NDP-9 layer onto DNTT leads to isolated clusters that coalesce into a continuous layer when more than 1 nm of NDP-9 is deposited. To confirm that doping with NDP-9 indeed increases the electrical conductivity of DNTT, we first fabricated TFTs with the dopant molecules deposited along the entire channel and in the contact regions. Comparing the transfer characteristics of TFTs without doping (Figure 3a) and with contact and channel doping (Figure 3b) shows that the channel doping greatly increases the off-state drain current. To rule out that the observed current increase is due to charge flow through the NDP-9, rather than through the DNTT, devices with 30 nm thick NDP-9 instead of DNTT were also made. SI, Figure S3, shows the current–voltage characteristics of such an NDP-9-only device. As can be seen, the current through the 30 nm-thick NDP-9 layer is below the leakage level, confirming that there is essentially no charge flow through the NDP-9 in this device. This confirms that charge flow in the DNTT TFTs with contact and channel doping (Figure 3b) occurs only through the DNTT and not through the NDP-9. Impact of channel doping and contact doping on the electrical characteristics of submicrometer TFTs (L = 150 nm, ΔL = 200 nm). a) Transfer and output characteristics of submicrometer TFTs without doping. b) Transfer and output characteristics of submicrometer TFTs with contact and channel doping. The transfer characteristics show that the channel doping greatly increases the off-state drain current (from <10−13 to about 10−9 A at VGS = 0 V), confirming that the dopant is electrically active and increases the excess carrier concentration in the semiconductor. The output characteristics show that the contact doping greatly increases the drain current at small drain–source voltages (VDS < VGS-Vth), which confirms that the doping reduces the width of the Schottky barrier at the contact/semiconductor interfaces, rendering the contacts essentially Ohmic. c) Transfer and output characteristics of submicrometer TFTs with contact doping (no channel doping). The transfer characteristics show a small off-state drain current and a large on/off ratio (similar to the TFTs without doping), while the output characteristics indicate Ohmic contact characteristics. Figure 3c shows the transfer characteristics (measured within 3 h after fabrication) of TFTs in which the dopant NDP-9 was deposited only in the contact regions, but not in the channel region. In this case the off-state drain current and the subthreshold swing are identical to those of TFTs without doping (Figure 3a), suggesting that the dopants do not drift or diffuse from the contact regions into the channel region during or shortly after transistor fabrication. Comparing the output characteristics of TFTs without doping (Figure 3a) and with contact doping (Figure 3c) reveals that contact doping with NDP-9 greatly increases the drain current at small drain–source voltages. For example, the drain current at VGS = -3 V and VDS = -0.5 V increases from -5 nA in the TFT without doping to -30 nA in the TFT with contact doping. This 6-fold increase in drain current is not due to a shift in threshold voltage, but due to a reduction in the width of the Schottky barrier at the contact/semiconductor interfaces, which means that a larger portion of the drain–source voltage drops along the channel, rather than across the contacts. Comparing the output characteristics in Figure 3a,c shows that contact doping also changes the shape of the measured ID–VDS curves closer to the 'ideal' linear shape. The above results confirm that NDP-9 acts as a p-type dopant in DNTT, which in turn confirms that electrons are transferred from the HOMO of DNTT to the LUMO of NDP-9, thereby creating excess holes in the DNTT and increasing the conductivity of the semiconductor. This suggests that at the interface between the evaporated DNTT and the evaporated NDP-9, the LUMO energy of NDP-9 is near or below the HOMO energy of DNTT. Since we cannot measure the orbital energies at the DNTT/NDP-9 interface, we have to rely on conclusions from other measurements to elucidate the energy lineup at the DNTT/NDP-9 interface. SI, Figure S4, summarizes the results of several measurements we have carried out to compare the doping strength of NDP-9 to that of an organic dopant that has been previously employed in organic TFTs, 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ).26, 27 We found that the sheet resistance of a 30 nm-thick DNTT layer doped with NDP-9 (nominally 1 nm thick) is a factor of 7 smaller than the sheet resistance of a 30 nm-thick DNTT layer doped with F4-TCNQ (also nominally 1 nm thick; SI, Figure S4a). In addition, our cyclic voltammetry measurements on NDP-9 and F4-TCNQ indicate that the LUMO energy of NDP-9 is more negative by 0.1 eV than the LUMO energy of F4-TCNQ (SI, Figure S4d). Since calculations and measurements by several other groups have shown that the LUMO energy of F4-TCNQ is approximately -5.2 eV,21, 22, 37, 38 this indicates that the LUMO energy of NDP-9 is about -5.3 eV and thus sufficiently low to allow charge transfer between the LUMO of NDP-9 and the HOMO of DNTT (for which an energy of -5.3 ± 0.1 eV has been determined by cyclic voltammetry and density functional theory;32 see SI, Figure S3c). The quantitative analysis of the contact resistance is often performed using the transmission line method (TLM).29 For TLM analysis it is assumed that the total resistance of a transistor (i.e., the resistance measured at the terminals of the transistor) is the sum of the channel resistance and the contact resistance. Neither the channel resistance nor the contact resistance are directly accessible, but both of them can be extracted by TLM analysis (see SI). However, TLM analysis produces useful results only if the parameter variations among the transistors are negligibly small. Unfortunately, the variations among our submicrometer TFTs are too large to permit TLM analysis (see SI, Figure S5a,b). Nevertheless, since the contact resistance cannot be larger than the total resistance, an upper limit of the contact resistance can be calculated simply by averaging the total resistance of a large number of transistors. For our sub­micrometer TFTs biased in the linear regime (VDS = -0.1 V) we obtain a total resistance of 9.8 kΩ cm for TFTs without doping and 2.7 kΩ cm for TFTs with contact doping (see SI, Figure S5c). To facilitate a more precise analysis of the contact resistance, we also fabricated long-channel top-contact TFTs with channel lengths ranging from 10 to 60 μm and with gate overlaps ranging from 5 to 200 μm. These TFTs were fabricated using macroscopic shadow masks.34 In these long-channel TFTs the relative contribution of the contact resistance is much smaller than in the submicrometer TFTs, so the mobility extracted from the current–voltage characteristics of the long-channel TFTs is much larger (≈2.2 cm2 V−1 s−1; SI, Figure S6) than that of the submicrometer TFTs (≈0.05 cm2 V−1 s−1; Figure 2). More importantly, the device-to-device variations in the long-channel TFTs are sufficiently small to allow TLM analysis (see SI, Figure S7). For TFTs without contact doping, we find a contact resistance of 0.66 kΩ cm. Contact doping reduces the contact resistance to 0.39 kΩ cm. The observation that the contact resistance of the submicrometer TFTs is significantly larger than that of the long-channel TFTs is explained by the difference in gate overlap. Assuming that charge flow between the source/drain contacts and the channel occurs only in those areas where the gate and the source and drain contacts overlap, the contact length is identical to the gate overlap (LC = ΔL). The current density across the contact/semiconductor interface is not constant, but has a maximum at the contact edge and decreases asymptotically in the direction away from the edge (see SI, Figure S8a). The transfer length (LT) is defined as the contact length over which 63% of the charge flow between contact and semiconductor occurs.29, 30 TLM analysis indicates a transfer length of 11 μm for the DNTT TFTs without contact doping (see SI, Figure S7). Calculations and measurements show that when LC is reduced below LT, the contact resistance increases dramatically, due to the loss of area available for charge flow (see SI, Figure S8b). This explains why TFTs with LC << LT (like our submicrometer TFTs) have larger contact resistance than TFTs with LC >> LT, (like our shadow-mask-patterned TFTs). It also shows that the choice of the gate overlap is a difficult trade-off between the requirement for a small contact resistance (which requires a large ΔL, so that ideally LC > LT) and the requirement for a small parasitic capacitance (which calls for the smallest manufacturable ΔL; see SI, Equation S4). More importantly, the TLM data show that contact doping significantly reduces the transfer length (from 11 to 5 μm; see SI, Figure S7). Contact doping is therefore a powerful tool to break the above-mentioned compromise and allow the simultaneous reduction of contact resistance and overlap capacitance (compare SI, Figure S8b,c). Again, this demonstrates the enormous potential of contact doping for submicrometer TFTs with patterned gate electrodes in high-frequency electronic applications. A major concern with area-selective doping in organic TFTs is the positional stability of the dopants. If the dopants were to drift or diffuse into the channel, the resulting channel doping would produce large off-state currents.24, 27, 28 Figure 4 shows results from a bias-stress measurement performed on a submicrometer TFT (channel length 150 nm) with contact doping. The TFT was stressed continuously for 1 h in air with the maximum possible gate–source voltage (VGS = -3 V, corresponding to a vertical electric field of 5.2 MV cm−1) and with the maximum possible drain–source voltage (VDS = -3 V; corresponding to a lateral electric field of 0.2 MV cm−1). The results indicate that bias stress does not lead to an increase of the off-state drain current nor to a loss of the linearity in the output characteristics, either one of which might be caused by dopants entering the transistor channel. These results confirm the positional stability of the organic dopant NDP-9 in the contact regions of the DNTT transistors. Bias-stress measurement on submicrometer TFTs (L = 150 nm) with contact doping. a) Transfer characteristics of a submicrometer TFT with contact doping before and after bias stress. During bias stress, a gate–source voltage of -3 V (corresponding to a transverse field of 5.2 MV cm−1) and a drain–source voltage of -3 V (corresponding to a lateral field of 0.2 MV cm−1) were continuously applied for 1 h. The results indicate that the dopant molecules incorporated into the contact regions of the TFTs do not drift or diffuse into the transistor channel, as this would lead to an increase in the off-state drain current or a loss of the linearity in the output characteristics. b) Drain current during bias stress over time. c,d) Output characteristics of the same device before (c) and after (d) bias stress. In summary, we have successfully employed aggressive gate-dielectric scaling and area-selective contact doping in order to efficiently suppress short-channel effects in nano­scale organic thin-film transistors that have channel lengths and gate overlaps of about 100 nm. We have shown that small off-state drain currents (about 10−13 A) and large on/off current ratios (107) can be achieved in submicrometer organic TFTs, provided that the thickness of the gate dielectric is scaled along with the channel length. A record transconductance of 0.4 S m−1 has been obtained for a TFT with a channel length of 90 nm and a gate overlap of 200 nm. We have also shown that contact doping with a strong molecular dopant significantly reduces the transfer length of the TFTs and is thus a powerful tool to simultaneously reduce the contact resistance and the parasitic overlap capacitance in organic TFTs. Contact doping has been found to reduce the contact resistance from 0.66 kΩ cm to 0.39 kΩ cm. Supporting Information is available from the Wiley Online Library or from the author. Detailed information on the fabrication process of the transistors and additional experimental data are available. The authors thank Bernhard Fenk at the Max Planck Institute for Solid State Research for preparing the transmission electron microscopy (TEM) lamella, Kersten Hahn and Peter van Aken at the Max Planck Institute for Intelligent Systems (formerly Max Planck Institute for Metals Research) for imaging and analyzing the TEM specimen, Richard Rook at CADiLAC Laser for providing high-quality shadow masks, and Klaus Kern at the Max Planck Institute for Solid State Research and the Ecole Polytechnique Fédérale de Lausanne for scientific guidance. The authors gratefully acknowledge financial support provided by the New Energy and Industrial Technology Development Organization (NEDO) of Japan. Detailed facts of importance to specialist readers are published as "Supporting Information". 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The analysis of transparent conducting oxide nanostructures suffers from a lack of high throughput yet quantitatively sensitive set of analytical techniques that can properly assess their electrical properties and serve both as characterization and diagnosis tools. This is addressed by applying a comprehensive set of characterization techniques to study the electrical properties of solution-grown Al-doped ZnO nanowires as a function of composition from 0 to 4 at. % Al:Zn. Carrier mobility and charge density extracted from sensitive optical absorption measurements are in agreement with those extracted from single- wire field-effect transistor devices. The mobility in undoped nanowires is 28 cm(2)/V s and decreases to similar to 14 cm(2)/V s at the highest doping density, though the carrier density remains approximately constant (10(20) cm(-3)) due to limited dopant activation or the creation of charge-compensating defects. Additionally, the local geometry of the Al dopant is studied by nuclear magnetic resonance, showing the occupation of a variety of dopant sites. (C) 2010 American Institute of Physics. [doi:10.1063/1.3360930]

An important prerequisite for the design of digital integrated circuits is the ability to control the threshold voltage of the individual transistors during manufacturing. To address the problem of controlling the threshold voltage of low-voltage organic transistors we have synthesized a fluoroalkylphosphonic acid that forms self-assembled monolayers on patterned, plasma-oxidized aluminum gate electrodes for use as high-capacitance, low-temperature gate dielectrics in p-channel and n-channel organic transistors. Compared with alkyl phosphonic acid-based monolayers, the strong electron-withdrawing character of the fluoroalkyl monolayers causes a change in the threshold voltage of the transistors by about 1 V, i.e. almost half of the supply voltage.

Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

The prospect of realizing nanoscale transistors using individual semiconducting carbon nanotubes offers enormous potential, both as an alternative to silicon technology beyond conventional scaling limits and as a way to implement high-speed devices and circuits on flexible substrates. A significant challenge is the realization of low-voltage nanotube transistors with individually addressable gate electrodes that display large transconductance, steep subthreshold swing, and large on/off ratio. Their integration into circuits with large signal gain and good stability still needs to be demonstrated. Here, we demonstrate that these important goals can be achieved with the help of a bottom-gate device structure that combines patterned metal gates with a thin gate dielectric based on a molecular self-assembled monolayer. The obtained transistors operate with a gate-source voltage of 1 V and have a transconductance of 5 microS, a subthreshold swing of 68 mV/decade, and an on/off ratio of 10(7). To verify the excellent operational and shelf life stability, we show that the device performance does not degrade during 10,000 switching cycles and during storage under ambient conditions for more than 300 days. We also demonstrate that the device structure allows the implementation of unipolar logic circuits with good switching characteristics.

We report on thin-film transistors based on ZnO nanoparticles processed from solution and with a maximum temperature of 100 degrees C. Electron mobilities up to 2.5 cm(2)V(-1)s(-1) are obtained, and top-gate TFTs show non-volatile memory properties with a large, stable hysteresis and a memory ratio of 10(5). Memory TFTs operate in ambient, have good shelf-life (>6 months), and useful endurance properties.