Tellurium (Te) is a promising p-type semiconductor but suffers from pronounced electrical hysteresis that limits device stability. The origin of hysteresis in Te field-effect transistors is investigated, and effective suppression strategies are demonstrated. In exposed devices, large hysteresis and abrupt current switching are observed, governed by the direction and range of gate voltage sweeps rather than gate polarity, and are attributed to the dynamic reorientation of dipolar gas molecules adsorbed on the Te surface. Dielectric encapsulation using Al2O3 significantly suppresses gas-induced hysteresis, resulting in improved mobility of similar to 80 cm(2) V-1 s(-1) and an I-ON/I-OFF ratio exceeding 10(5) under ambient conditions. Nevertheless, residual hysteresis associated with charge trapping persists in single-gate devices. To further stabilize channel electrostatics, a dual-gate architecture employing Al2O3 top and bottom dielectrics is implemented, achieving hysteresis below 1 V across a wide range of sweep rates and exhibiting minimal degradation under prolonged bias stress. These results establish a comprehensive understanding of hysteresis in Te and enable reliable, BEOL-compatible p-type transistors for advanced integration.

Amorphous oxide semiconductors offer a unique platform for versatile device processing, as their noncrystalline nature eliminates the requirement for lattice matching at the interface and enables low-temperature regrowth and isotropic processing. Leveraging chemical continuity of amorphous surface, this study demonstrates atomic-scale, reversible thickness control of amorphous In2O3 by integrating bottom-up atomic layer deposition with top-down hydroxide-assisted wet-etching processes. The processes achieve bidirectional modulation of the film thickness from 1 to 4 nm under back-end-of-line compatible conditions while maintaining smooth surfaces (Ra = ∼0.5 nm) and stable chemical composition. This thinning-regrowth process enables precise, thickness-dependent control over the In2O3 transistor performance, facilitating doping-free modulation of the threshold voltage and reversible switching between depletion- and enhancement-mode operation within a single device. Successful demonstration of inverters and ring oscillators confirms the robustness of this technique, establishing film thickness as a core design parameter for oxide semiconductors and paving the way for reconfigurable electronics.

Percolation transport dominates the charge conduction in amorphous and polycrystalline semiconductors. This study identifies a dimensional scaling effect unique to transistors using percolative semiconductors as channel materials, where the materials' percolation threshold (p c) exhibits a strong correlation with the transistor threshold voltage (V T). We demonstrate that both parameters are fundamentally governed by the semiconductor channel geometry. By reducing channel thickness, width, or length, p c is modulated because the availability of conductive pathways is constrained by the channel dimensions, directly driving the observed V T shifts. A quantitative link between p c and V T is established through the percolation potential landscape visualized by scanning tunneling microscopy. The result reveals that the energy landscape is determined by the Fermi level, a characteristic of percolative channels, where device turn-on occurs as the Fermi level exceeds the potential barriers to form conductive pathways. This mechanism is confirmed by temperature-dependent transport measurements, where the extracted activation energies exhibit a strong geometric dependence consistent with the p c and V T shifts. This scaling effect appears consistently in both n-type In2O3 and p-type SnO transistors, showing its universality across percolative semiconductors regardless of the carrier type. These findings demonstrate that transport in amorphous semiconductor devices is defined by percolation-governed transport rather than conventional electrostatics or quantum confinement, and establish geometry as a key design parameter for future amorphous electronics.

Monolithic three-dimensional integration enables dense vertical stacking of devices with fine-pitch interconnects, offering a promising route toward high-density, energy-efficient logic and memory systems. However, its implementation is constrained by the thermal budget of back-end-of-line processes, which must remain below 400 °C to avoid degrading underlying circuitry. While various low-temperature semiconductors have been explored, current demonstrations remain confined to fixed stacking sequences due to high-temperature growth or transfer requirements. Here, we demonstrate a M3D complementary field-effect transistor architecture using low-temperature-deposited n-type In2O3 and p-type Te semiconductors. This platform resolves existing thermal constraints, demonstrating the design freedom to reverse n- and p-type sequences. This capability enables the integration of CMOS inverters, multilayer logic stacks, and a fully functional 3D SRAM storage cell, all fabricated below 300 °C. This scalable platform provides a practical pathway for constructing vertically integrated complementary logic with intrinsic interconnects, paving the way for next-generation 3D system-on-chip technologies.

Oxide semiconductors have gained substantial interest for their low-temperature processability, allowing for their integration as functional add-on device layers for advanced monolithic 3D integrated circuits (ICs). However, reliability issues, particularly under thermal, environmental, and electrical stresses, remain critical issues and require immediate solutions. This study investigates the instability of ultrathin In2O3 transistors, revealing that threshold voltage (VT) drifts arise from interactions between surface-adsorbed oxygen and the In2O3 channels. We show that the oxygen in the ambient atmosphere attached to the In2O3 surface plays a crucial role in modulating In2O3 conductivity, thereby governing VT. External perturbations such as ultraviolet (UV)/X-ray illumination, thermal annealing, and bias stress could alter this interaction of surface oxygen with ultrathin In2O3, leading to a VT drift. Importantly, we propose a unified kinetic model that provides a generic physical description of VT instabilities induced by these commonly observed factors. By characterizing time-dependent VT instability, the model demonstrates that recovery dynamics exhibit identical behavior across all tested perturbations, indicating that the recovery process is independent of the initial stimulus. This study uncovers the surface oxygen as a critical factor affecting In2O3 transistor reliability, offering insights for designing oxide-based devices for advanced electronic and optoelectronic devices.

ABSTRACT Two‐dimensional materials with piezoelectricity and polarization‐enabled electromechanical responses provide a promising basis for multifunctional electronics, including memory devices and neuromorphic computing. In this work, we explore cryogenic physical vapor deposition (cryogenic PVD)–grown TexSe1‐x thin films, a tellurium‐based compound with a tunable bandgap and enhanced non‐centrosymmetry, and examine their polarization‐associated electromechanical characteristics. A 10 nm Te0.9Se0.1 film exhibits a clear switchable electromechanical response with a piezoelectric coefficient d33 of 33 pm/V, together with stable piezoresponse under ambient conditions. Introducing a Se ratio of 0.1 is found to enhance the polarization behavior and domain response while maintaining the crystalline quality of the TexSe1‐x films. Memory devices based on Te0.9Se0.1 show retention beyond 2000 s and remain switchable up to 1000 cycles, with an HRS/LRS ratio exceeding 102 under ± 20 V program/erase pulses when read at a drain voltage of 1 V. In addition, synaptic behavior is demonstrated with 92% image recognition accuracy at low energy consumption, suggesting potential for neuromorphic applications. These results highlight the potential of TexSe1‐x films as a polarization‐enabled piezoelectric semiconductor system for future low‐power memory and computing applications.

Oxide semiconductors such as indium oxide (In2O3) offer high-electron mobility and low-temperature processability, making them promising candidates for back-end-of-line (BEOL)-compatible logic-in-memory applications. However, direct deposition of high-κ ferroelectric dielectrics (Hf0.5Zr0.5O2; HZO) on oxide channels typically degrades interfacial quality, leading to threshold voltage shifts and unstable polarization due to depolarization fields and defect states. In this work, we leverage advanced membrane transfer techniques to demonstrate a transferable ferroelectric HZO layer for interface-layer-free integration with In2O3. This approach forms a van der Waals-like junction, evidenced by an ∼0.8 nm interfacial gap, which avoids the chemical incompatibilities of conventional gate stack processing while preserving the pristine stoichiometry of the In2O3 channel. The transferred HZO exhibits a dielectric constant of 26 and low leakage current (<10-7 A cm-2 at 1 MV cm-1) while maintaining robust ferroelectric switching. Dual-gate ferroelectric In2O3 transistors achieve a large memory window and stable endurance over 109 cycles. We further integrate these devices into reconfigurable inverter circuits that dynamically switch between NOR and NAND logic functions with tunable voltage transfer characteristics. The ferroelectric thin-film transfer process is fully compatible with silicon back-end-of-line thermal budgets and scalable to wafer-level integration, offering a viable route toward high-density, multifunctional logic-in-memory architectures.

High-performance DUV spectroscopy drives advancements in biomedical research, clinical diagnosis, and material science. Existing DUV resonant nanostructures face instability and photoluminescent noise challenges. We propose robust Si metasurfaces leveraging polaritonic resonances, a unique property driven by interband transitions, for enhanced nanophotonic sensing. Our polaritonic Kerker-type void metasurface enables double-resonance Raman scattering to analyze 2D semiconductors, improves biomolecule autofluorescence, and offers superior stability. This scalable platform unlocks versatile applications in interdisciplinary DUV spectroscopy and emerging nanomaterials research.

High-performance deep ultraviolet (DUV) spectroscopy is crucial in driving innovations for biomedical research, clinical diagnosis, and material science. DUV resonant nanostructures have shown capabilities for significantly improving spectroscopy sensitivity. However, they encounter significant challenges in practical applications, including instability due to oxidation and light-induced damage, and the strong photoluminescent noise background from their constituent materials. An efficient and robust DUV spectroscopy platform based on the polaritonic properties in all-dielectric silicon (Si) metasurfaces is proposed. Unlike conventional dielectric metasurfaces that rely on Mie-type modes, this approach leverages the polaritonic resonances in Si nanostructures-a striking yet underexplored property driven by interband transitions in the DUV regime-for nanophotonic sensing. A polaritonic Kerker-type void metasurface providing strong near-field enhancement localized on the surface is designed and fabricated. The metasurface facilitates double-resonance Raman scattering, a process that reveals key information about lattice dynamics and electronic structures, for analyzing 2D semiconductor monolayers. It also demonstrates superior stability in solvents and enhances biomolecule autofluorescence. These capabilities demonstrate the versatile potential of Si metasurfaces as a scalable, robust platform for interdisciplinary DUV spectroscopy applications, including advanced biomedical research and the investigation of emerging nanomaterials.

Ultrathin indium oxide films show great potential as channel materials of complementary metal oxide semiconductor back-end-of-line transistors due to their high carrier mobility, smooth surface, and low leakage current. However, it has severe thermal stability problems (unstable and negative threshold voltage shifts at high temperatures). In this paper, we clarified how the improved crystallinity of indium oxide by using ultrahigh-temperature rapid thermal O2 annealing could reduce donor-like defects and suppress thermal-induced defects, drastically enhancing thermal stability. Not only does more crystalline indium oxide depict the high stability of threshold voltage in stringent high-temperature test environments and under positive bias, but it also shows much less degradation under forming gas annealing than as-deposited transistors. Furthermore, we also successfully solved the channel length-dependent threshold voltage problem, which is often observed in oxide transistors, by suppressing defects induced by the metal deposition process and metal doping.

High-energy metal deposition significantly impacts the performance and reliability of two-dimensional (2D) semiconductors and nanodevices. This study investigates the localized annealing effect in atomically thin In2O3 induced during high-energy metal deposition. The localized heating effect alters the electronic performance of In2O3 devices, especially in shorter channel devices, where heat dissipation is further constrained. This effect creates a conductivity gradient along the In2O3 device with higher conductivity near the metal contact, as observed by conductive atomic force microscopy (C-AFM). This gradient leads to a pronounced threshold voltage (Vth) shift as the channel length (Lch) decreases, resembling a short-channel effect but one driven by thermal mechanisms rather than conventional mechanisms. Furthermore, metals with higher latent heats can exacerbate these effects. We also show that reversing the deposition sequence and postdeposition oxygen annealing effectively suppress Vth shifts across different Lch. This work offers key insights into controlling thermal effects during fabrication to improve ultrathin oxide transistor performance.

Here, a pulsed laser annealing (PLA) process is employed to enhance the crystallinity and functional performance of tellurium (Te) thin-film devices. The PLA facilitates localized melting followed by rapid cooling, which promotes recrystallization while significantly reducing energy loss compared to conventional thermal annealing techniques. Field-effect transistors (FETs) incorporating a PLA-treated Te film (10 nm) demonstrate a hole mobility of 107.9 cm2 V-1 s-1 and a substantially improved on/off current ratio, underscoring their suitability for high-performance electronic applications. Photodetectors based on the PLA-treated Te film (10 nm) exhibit exceptional photoresponsivity of 72.94 A W-1 under light illumination with a wavelength of 408 nm, along with faster response time and improved detectivity, reflecting their enhanced optoelectronic functionality. For gas sensing measurements, PLA-treated Te (10 nm) sensors achieve a nitrogen dioxide (NO2)response of 55.4% at 1 ppm, with rapid response and recovery times of 0.92 and 27.7 s, respectively. For detecting hydrogen sulfide (H2S) gas, the response improves to 98.3% at 10 ppm, with response and recovery times of 121.3 and 78.8 s. These improvements are attributed to the enhanced crystallinity, enlarged grain sizes, and smoother surface morphology induced by the PLA process.

In this paper, we present a five-layer polymer-based interposer technology using inkjet printing to fabricate silver vertical through-substrate vias (TSVs) for beyond 5G and edge-AI applications. Photosensitive epoxy resin (PESP) and polyimide (PSPI) are employed as low- loss dielectric materials, providing excellent thermal and mechanical stability. High-frequency measurements of microstrip line structures demonstrate good performance, with characteristic impedance close to 50 Omega and low insertion loss at 94 GHz. In addition, strong agreement between measurement and simulation results of a 79 GHz substrate-integrated waveguide (SIW) antenna confirms the feasibility of the proposed design. Compared with conventional interposer technologies, this approach offers a lightweight, low-cost, and high-performance solution for advanced heterogeneous integration, particularly in edge-AI sensing and high-frequency communication systems.

Achieving symmetric $\mathrm{n} / \text{pFETs}$ with high current densities and matched threshold voltages in a single 2D channel material is crucial for homo-channel CMOS integration and the realization of 3D monolithic applications. This work introduces novel n-doping using aluminum nitride (AlN) and p -doping using molybdenum oxide ($\text{MoO}_{\mathrm{x}}$) on CVD-grown monolayer tungsten diselenide ($1 ~\mathrm{L}-\text{WSe}_{2}$), achieving record-high electron current ($\sim 230 \mu ~\mathrm{A} / \mu \mathrm{m}$ at $\mathrm{V}_{\text{DS}}=1 ~\mathrm{V}$) with lowest contact resistance ($\sim 1 \mathrm{k} \Omega \cdot \mu \mathrm{m}$) and one of the best reported hole currents ($>400 \mu ~\mathrm{A} / \mu \mathrm{m}$ at $\mathrm{V}_{\text{DS}}=-1 ~\mathrm{V}$), both in enhancement mode. AlN/MoO ${ }_{x}$ doping enables tunable doping strength with on/off ratio ($>10^{6}$) and well-matched $\mathrm{V}_{\text{TH}}$ for n - and pFETs. This work demonstrates high gain ($>25 ~\mathrm{V} / \mathrm{V}$ at $\mathrm{V}_{\text{DD}}=1.5 ~\mathrm{V}$) and the potential of $\text{WSe}_{2}$ for mono-channel CMOS technology.

Colloidal quantum dots (CQDs) are nanocrystals synthesized in solution, boasting remarkable optical properties and notable electronic characteristics, such as size‐tunable bandgaps and high photoluminescence quantum yield. These features, coupled with solution processability, position CQDs as potential candidates for cost‐effective and high‐performance optoelectronic devices. However, several technological challenges hinder the full exploitation of CQDs in optoelectronics. Among these is the need for long insulating organic ligands in liquid‐phase synthesis, which restrict efficient charge injection and transport in quantum dot (QD) films. Furthermore, the high surface‐to‐volume ratios and core–shell structures prompt complexities in terms of doping and modifying electronic properties. The colloidal nature of quantum dots (QDs) also raises challenges regarding controlled deposition and patterning, which are critical for device fabrication. In this review, the imperative is outlined to tailor CQDs for optoelectronic applications, the limitations that obstruct the implementation of desired modifications are elaborated on, and the specific hurdles confronting electronic coupling, targeted doping, and precision patterning of CQDs are focused on. Additionally, herein, a summary of the solutions proposed to date is offered, insights are shared on the discussed topics, and areas warranting future investigation are highlighted.

Achieving efficient electroluminescence (EL) in 2D materials requires precise control over the injection and recombination of charge carriers-electrons and holes. In this study, a method is introduced to improve charge carrier injection in using transition metal dichalcogenides (TMDCs) based light emitting devices driven by alternating current (AC), achieved through dual pulse injection. The dual pulse device exhibits a notable enhancement in EL intensity, displaying a substantial increase as compared to the single pulse device, achieving an approximate sixfold improvement. The proposed dual pulse operated device configuration enables the independent control of electron and hole injection, facilitating the fine-tuning of carrier recombination processes to improve the EL emission efficiency. Phase delay dependent EL characteristics are observed featuring a maximum integrated EL at a phase delay of 180 degrees indicating an enhanced EL emission during out-of-phase pulse operation between the electrodes. Moreover, the dual pulse device exhibited a approximate to 3.5-fold improvement in the device EL external efficiency (eta e) when compared to the device operated with a single pulse. Manipulating carrier recombination in TMDCs-based LEDs opens up new opportunities to enhance their performance, enabling practical applications in display technology, lighting, optical communication, and electrically tunable light sources.

In the past few years, there has been a significant emphasis on atomically-thin metal oxide semiconductors (OS), driven by their adjustable electrical properties that open up a range of electronic applications [1.2]. However, the mechanisms of transport and electronic tunability in OS remain unclear [3]. X-ray characterization techniques, i.e. X-ray photoelectron spectroscopy (XPS) and X-ray diffractometer (XRD), are considered as non-destructive and are widely used to quantify the chemical and electronic state of OS. In this work, we discovered that X-ray has significant impact on the electronic properties of OS. We observed that low energy X-ray (<2 keV) induces a negative V T offset in OS devices [4]. The variation in V T primarily originates from the chemical interaction of oxygen molecules on the channel surface. OS devices absorb the low-energy X-ray, generating the holes, and they subsequently react with O 2 - on the channel surface, resulting in the production of oxygen and its removal from the channel surface, as shown in Fig 1a. The V T shift caused by low energy X-ray will recover in air over time, as illustrated in Fig 1b. We incorporated the post low-energy X-ray devices into a vacuum environment with a pressure of 10 -6 torr, and the V T of the device exhibited no recovery over time, providing additional support for oxygen absorption mechanism. Time-resolved electrical measurements conducted in different atmospheric conditions reveal that the variations in V T arise from the oxygen absorption mechanism. The research highlights the effect of X-ray on OS and analyzes the mechanism behind the increase in OS carrier concentration induced by the X-ray exposure. [1] Si, M. et al. Scaled indium oxide transistors fabricated using atomic layer deposition. Nat. Electron. 5, 164–170 (2022). [2] Charnas, Adam, et al. Extremely Thin Amorphous Indium Oxide Transistors. Adv. Mater. 2304044 (2023). [3] Conley, J. F. Instabilities in amorphous oxide semiconductor thin-film transistors. IEEE Trans. Device Mater. Rel. 10, 460–475 (2010). [4] Tseng, R., Wang, ST., Ahmed, T. et al. Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors. Nat. Commun. 14, 5243 (2023). Figure 1