The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) technology. Especially, compressive SiGe channel has been demonstrated to enhance hole mobility and therefore pMOSFETs drive currents. At the same time, the performance gain induced by this mechanical stressor comes along with layouts effects. In this study, we characterize experimentally the impact of the active region dimensions and shape on the threshold voltage and linear drain current of SiGe channel pMOSFETs directly on insulator fabricated for the 14nm technology node. The pMOS threshold voltage increases by 105mV for a gate-to-STI distance of 80nm compared to 980nm while IODLIN decreases by 51%. An analytical model is proposed to reproduce the layout dependences. The model is based on the stress profile, taking into account both the stress from the SiGe channel and from SiGe source/drain. It reproduces the experimental data with a good accuracy in the cases of symmetric and asymmetric layouts, provided a typical relaxation length of 112nm is used. Finally, a special attention is paid on multifinger transistors, since they are widely used in standard cells designs.

In this paper we discuss the specific challenges of process integration of Si-Photonics for the current and future applications, including lithography, etching and heterogeneous materials integration.

We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows −39% mobility for 170nm narrow 2µm long channel, but +21% Ieff at Lg=20nm and gate-to-STI distance of 59nm. It is translated into a −15% delay reduction for ring oscillators of 1-finger inverters. Layout dependences are explained by physical strain measurements and reproduced by a stress-based electrical model.

A novel dual isolation scheme with both Shallow Trench Isolation (STI) and local oxidation, so called Dual Isolation by Trenches and Oxidation (DITO), is presented to maximize the stress induced by SiGe channel and the back-biasing efficiency at the same time in FDSOI technology. DITO integration experimentally demonstrates +36% pMOSFET drive current at same leakage, which is translated into −23% ring-oscillator delay reduction at a supply voltage of V dd =0.8V. It is found that this gain is attributed to 0.45GPa saved compressive stress in the longitudinal direction, compared to the standard STI isolation. On top of that, DITO enables the Vt tuning in an extended range for both nMOS and pMOS independently through back-bias application in both reverse and forward modes. +29% and 1 decade leakage extensions are provided by this full range Vt tuning compared to the standard single STI and well FDSOI architecture where only one back-bias mode is allowed. DITO thus leverages highly-stressed and highly-tunable devices for both high performance and low power applications.

We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core.

We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-performance at the 14nm node. At the same time, it induces strong layout effects, which are reported and explained in this paper. They can be reproduced by an accurate physics-based electrical model, which enables us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading experimentally to a -15 percent delay reduction for a ring-oscillator of 1-gate finger inverters at 0.8V supply voltage. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Namely, a continuous-RX design, which consists in a long active line configuration, optimizes the stress configuration, maintaining a high level of longitudinal compressive stress, while relaxing the transverse one. A 28 percent ring oscillator delay improvement is experimentally demonstrated at a given leakage for 1-finger inverter at 0.8V supply voltage. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. Finally, we discuss the technological knobs and especially the strain boosters that can furthers the scaling of FDSOI below the 14nm node: SiGe channel and source/drain of high-Ge content, influence of the surface orientation and channel direction, as well as the gate last integration.

The introduction of SiGe channel for pMOSFETs in FDSOI technology enables to achieve high performance. However, it has been demonstrated that such a global stressor induces layouts effects. In this paper, we present an exhaustive study of layout impact on threshold voltage. Especially, dissymmetric layouts, non-rectangular active areas and multifinger transistors are investigated. We propose an analytical model based on stress profile to reproduce the layout dependences. This model reproduces the experimental data with good accuracy, whatever the shape of the active area.

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

300 mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5 nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge enrichment technique. Those substrates will be used as the channel of advanced Fully Depleted (FD) p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFET). We present in the first part the successful fabrication of 5 nm SGOI wafers. Various characterization techniques are used to investigate the Ge profile and the final strain in the fabricated 5 nm Si0.7Ge0.3 film. Secondary Ions Mass Spectrometry (SIMS) and Scanning Transmission Electron Microscopy (STEM) clearly show that the Ge content is very homogeneous (xGe = 30 ± 1%) in the SiGe layer. Raman spectroscopy and High Angle Annular Dark Field (HAADF) STEM both confirm that the 5 nm thick SiGe film is compressively strained (−2 GPa). The second part is dedicated to the sensitivity of the Ge enrichment process (based on numerical modelling). We investigate the impact of single and combined fluctuations of the pre-structure parameters (TSi, TSiGe,0, xGe,0) on the final SiGe layer (TSiGe, xGe).

Ge condensation using RTO is investigated to produce good quality SGOI channel. This study shows the significant role of the RTO temperature in Ge condensation. First, Ge diffusion requires a RTO temperature above 950°C to start homogenization of Ge in the channel. This is mandatory to minimize the risk of defects generation. Then, inconsistently to thermodynamics calculation, Ge-O bounds are formed during oxidation and a higher temperature oxidation leads to a lower Ge-O bounds formation. Therefore, Ge condensation using a 1100°C RTO is preferred. It is implemented in a SOI/SGOI co-integration to produce SGOI channel for PMOS transistor. Such channel exhibits a very smooth surface (RMS roughness below 0.15nm), a controlled Ge content (16%) and a high compressive strain (1%). Moreover, PMOS Vt modulation by the Ge concentration was performed with a sensitivity of 10mV/%. As a result, this study demonstrates that RTO is a solid alternative to furnace for Ge condensation.

High mobility channels are considered as an interesting path to increase PMOS performances for advanced CMOS technology. Silicon-Germanium On Insulator (SGOI) benefits from both the advantage of the SiGe material (hole mobility booster) and the On Insulator structure (better electrostatic control of the channel by the gate) [1]. The co-integration of NMOS and PMOS, respectively on Silicon On Insulator (SOI) and SGOI zones, can be enabled easily by the Ge condensation technique [1,2]. This technique is based on the competition between Ge diffusion and Si oxidation which are both driven by temperature. For this purpose, mainly furnace oxidation is reported in the literature [1-3]. In this work, we propose to study Ge condensation using Rapid Thermal Oxidation (RTO) as an alternative process. SGOI structures were fabricated on 300mm SOI wafers, with 11nm thick top silicon. First, epitaxy layers of SiGe were grown with varying thickness (from 3 to 10nm) and Ge concentration (from 10 to 40%). The SiGe film was grown by Rapid Thermal Chemical Vapor Deposition at temperature between 600°C and 650°C. Then, Ge condensation was performed by RTO in O 2 ambient at temperatures between 950°C and 1150°C. Both aspects of Ge condensation were studied: Ge diffusion then Si oxidation. The RTO temperature effect on Ge diffusion was analysed by ToF-SIMS (Figure 1). In the case of short oxidation duration (below 2 minutes), as typically used in RTO compared to furnace (several hours), almost no diffusion is observed at 950°C. This leads to Ge enrichment of the initial SiGe layer with Ge concentration gradient. For longer oxidation, this might result in very high Ge concentration generating strain relaxation via stacking fault creation [4]. Therefore, temperatures above 950°C are prefered to avoid defects creation. TEM and STEM-EDX of the structure after condensation (Figure 2) shows that Ge concentration is still not totally homogeneous at 1100°C. Oxidation kinetics is shown on Figure 3, comparing the effect of substrate: SiGe/Si/BOX vs Si. SiGe is oxidized faster than Si, as already reported [5,6]. Moreover, SiGe oxidation is enhanced with increasing Ge concentration. Same trend is observed concerning SiGe thickness, indicating the effect of Ge diffusion in the underneath Si layer. A compositional analysis of the oxide grown by condensation was performed by XPS, monitoring the Ge3d peak (Figure 4). Starting from the same SiGe/Si/BOX structure, the oxide thickness was kept the same using different RTO temperatures but tuning the O 2 pressure and the RTO duration. The effect of Ge diffusion is clearly observed by the intensity of the Ge-Si contribution. Higher temperature leads to lower Ge concentration due to a more homogeneous Ge distribution. Surprisingly, Ge-O bounds are also observed, whereas Si x Ge 1-x alloy oxidation is thermodynamically considered to be Si selective [7]. Moreover, the amount of Ge-O bounds increases when the RTO temperature decreases. As shown previously, low temperature oxidation leads to high Ge concentration at the SiO2/SiGe interface, which may enable the formation of Ge-O bounds [8]. As a consequence, oxidation kinetics plays an important role in this phenomenon. This study reveals the significant role of temperature in Ge condensation by RTO. Due to kinetics effect, Ge-O bounds are formed which is not predicted by thermodynamics. Finally, the role of temperature will be investigated through electrical characterization of the Si x Ge y O properties. [1] B. Vincent at al, Mat. Sc. Semicond. Proc. 11, 2008 [2] T. Tezuka et al., Jpn. J. Appl. Phys. 40, 2886, 2001. [3] Z. Di et al., J. Crystal Growth 281, 2005 [4] B. Vincent, Appl. Phys. Lett. 90, 2007 [5] O. W. Holland et al., Appl. Phys. Lett. 51, 7, 1987 [6] S. J. Kilpatrick et al., J. Appl. Phys. 81, 12, 1997 [7] D. C. Paine et al, J. Appl. Phys. 70, 5076, 1991 [8] J. Eugene, Appl. Phys. Lett. 59, 78, 1991

We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.

This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher speed or active power mitigation. This technology has been developed on the (100)-oriented substrate with a key focus on process simplicity. Transistor improvement relies on mask-free strain engineering techniques along with co-implanted halos and laser anneal. The impact of laser anneal on transistor reliability and mixed-signal capabilities are also examined. Drive current as high as 660/320 muA/mum at 1nA/mum and 1.1V are reported

Thermal flow process with a PSM reticle was studied here in order to print a 300mm wafer with dense 120nm contact holes patterns (260nm pitch). This technique is accomplished by a feature size shrinkage using a post development bake. Thus larger features than the final etched ones can be printed which helps maintaining a workable process window. The resist used along this study (XP 11016) is particularly designed for thermal reflow applications by some built-in material properties: (1) Tight polymer molecular weight dispersity for good thermal flow control. (2) Optimized PAG characteristics to get good contact holes resolution and wide process window. (3) Additives to keep contact holes profiles through reflow steps. This study presents a method to defined process setting for different pitches using thermal flow and OPC. The effect of post development bake temperature on resist shrinkage, etch resistance and CD shrinkage was evaluated. Different sizing bias, reflow temperature and optical settings were studied in order to choose the best conditions to print dense or isolated features and finally extract the best overlapping results. The settings obtained using an empirical model make possible to print simultaneously 120nm dense and isolated contact holes.