We successfully developed new devices and new features in the 18nm FDSOI technology for addressing the low power and the low leakage demands of Micro-Controller Units (MCUs). In a quadruple fully mixable Vt offer, 80% speed enhancement and 2x leakage reduction are demonstrated at $0.6 V V_{dd}$ vs the fastest and vs the less-leaky 28nm FDSOI devices, respectively. Low leakage device options have been built for all device families of this Triple Gate Oxide (TGO) platform (i.e thin: SG – medium: EG – thick: eZG), achieving 10pA/μ m for SG/EG transistors and 1pA/μm Idoff for 3.3V eZG ones without adding any mask nor process cost. For SRAM, the high-density $0.102 \mu m^{2}$ SRAM bitcell has been carefully optimized and, in addition, an innovative Zero-power $0.532 \mu m^{2}$ SRAM (ZpSRAM) is proposed for the first time. As a result, record-low retention leakage of 0.6pA/cell and 30fA/cell are reported respectively for those two bitcells, completing the list of benefits brought to the 18nm FDSOI device suite to fulfill ULP/ULL design requirements.

For the first time in the industry, 18nm FDSOI technology platform meeting the performance target for next MCU is presented based on triple gate oxide and HKMG process. To meet the performance target of next MCU, continuous-active and device width increase by “contact on gate over active” with wide process margin are utilized. Good yield in 64Mb SRAM array for all SRAM bitcells (bitcell area 0.102um2 and 0.124um2 for ultra low leakage and high speed, respectively) including ultra low leakage bitcell with retention leakage under 1pA is confirmed. 500hrs HTOL for all SRAM bitcells and WLR for all SG/EG/eZG in TGO are passed. ePCM (embedded Phase Change Memory) is co-integrated in 18nm FDSOI process as non-volatile memory option.

We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core.

A new technological platform aimed at making prototypes and feasibility studies has been setup at STMicroelectronics using 300mm wafer foundry facilities. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is devoted at developing and evaluating new devices and sub-systems in particular for wavelength division multiplexing (WDM) applications and ring resonator based applications. Developed in the course of PLAT4M-FP7 European project, DAPHNE is a flexible platform that fits perfectly R&D needs. The fabrication flow enables the processing of photonic integrated circuits using a silicon-on-insulator (SOT) of 300nm, partial etches of 150nm and 50nm and a total silicon etching. Consequently, two varieties of rib waveguides and one strip waveguide can be fabricated simultaneously with auto-alignment properties. The process variability on the 150nm partially etched silicon and the thin 50nm slab region are both less than 6 nm. Using a variety of different implantation configurations and a back-end of line of 5 metal layers, active devices are fabricated both in germanium and silicon. An available far back-end of line process consists of making 20 mu m diameter copper posts on top of the electrical pads so that an electronic integrated circuit can be bonded on top the photonic die by 3D integration. Besides having those fabrication process options, DAPHNE is equipped with a library of standard cells for optical routing and multiplexing. Moreover, typical Mach-Zehnder modulators based on silicon pn junctions are also available for optical signal modulation. To achieve signal detection, germanium photodetectors also exist as standard cells. The measured single-mode propagation losses are 3.5 dB/cm for strip, 3.7 dB/cm for deep-rib (50nm slab) and 1.4 dB/cm for standard rib (150nm slab) waveguides. Transition tapers between different waveguide structures are as low as 0.006 dB.

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

The main difficulty related to DoseMapper correction is to generate an appropriate CD datacollection to feed DoseMapper and to generate DoseRecipe in a user friendly way, especially with a complex process mix.We could heavily measure the silicon and create, in feedback mode, the corresponding DoseRecipe. However, such approach in a logic fab becomes a heavy duty due to the number of different masks / product / processes. We have observed that process CD variability is significantly depending on systematic intrawafer and intrafield CD footprints that can be measured and applied has generic pre-correction for any new product/mask process in-line. The applied CD correction is based on a CD (intrafield: Mask + Straylight & intrawafer: Etch Bias) variability "model" handled by the FAB APC (Advanced Process Control).Individual CD profile correction component are generated "off-line" (1) for Intrafield Mask via automatic CD extraction from a Reticle CD database (2) for Intrafield Straylight via a CD "model" (3) for Intrawafer Etch Bias via engineering input based on process monitoring.These CD files are handled via the FAB APC/automation system which is remotely taking control of DoseMapper server via WEB services, so that CD profiles are generated "off-line" (before the lot is being processed) and stored in a profile database while DoseRecipes are created "real-time" on demand via the automation when the lot comes to the scanner to be processed. DoseRecipe and CD correction profiles management is done via the APC system.The automated DoseRecipe creation is now running since the beginning of 2011 contributing to bring both intrafield and intrawafer GATE CDu below 1nm 3sigma, for 45/40 & 28nm nodes.

A novel parameter extraction method is proposed to dissociate the current contributions of each channel in 3D Gate-All-Around multi-channel transistors. These devices, designed for CMOS low standby power architectures, exhibit well behaved characteristics and high performance. Our methodology is based on systematic measurements, numerical simulations and modeling. The substrate bias technique is used to turn ON and OFF the various channels and to remove the bottom channel contribution from the total measured current. Very high I ON /I OFF ratios (NMOS: 2.27 mA/μm for 16 pA/μm; PMOS: 1.32 mA/μm for 16 pA/μm) are obtained experimentally as a benefit from good short-channel mobility values in each type of channel. A mobility reduction is observed in long-channel GAA transistors.

Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO 2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO 2 and N + poly-Si/SiO 2 gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high- kappa/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D silicide position.

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations associated to such devices integration as well as their potential applications.

Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow IOFF (16 pA/mum) and high ION (N: 2.27 mA/mum and P: 1.32 mA/mum) currents are obtained on silicon on insulator (SOI) with a high-kappa/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-kappa/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher VDsat for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I ON /I OFF characteristics (NMOS: 2.33 mA/mum at 27 pA/mum and PMOS: 1.52 mA/mum at 38 pA/mum). A gate capacitance C gg reduction of 32% is measured, thanks to S -parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain A VI ( = gm / g ds ) is improved by 92%.

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (g(m)) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A(VI)) and early voltage (V-EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (f(T)), due to the large total input gate capacitances (C-GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C-GG and f(T). The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

A novel parameter extraction method is proposed to dissociate the current contributions of each channel of highly performing Multi-Channel CMOS Low Standby Power architecture. It is shown that the very high I-ON/I-OFF ratio (NMOS: 2.27mA/mu m for 16pA/mu m PMOS 1.32mA/mu m for 16pA/mu m) obtained experimentally benefits from good short-channel mobility values of each type of channel despite a limited degradation of the GAA mobility value.

Both CMOS scaling and NEMS sensor devices scaling converge to the same type of sub 100 nm objects. This opens new fields of application for IC chips integrating both complex signal treatment and very highly sensitive sensing functionalities.

Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.

For the first time, ultra low IOFF (16.5 pA/mum) and high IONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best ION/IOFF ratios ever reported: 1.4 times 108 (0.8 times 108) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods and analytical modeling, how those performances are obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.