This work investigates the impact of CMOS scaling on the DC effective drive current, $I_{eff}$ [1], $I_{eff}=1/2\times(I_{high}+I_{low})=1/2\times [d_{s}(V_{gs}=0.5V_{dd},V_{ds}=V_{dd})+(V_{gs}=V_{dd},V_{ds}=V_{dd}/2)$ ] of aggressively scaled MOSFETs down to 7nm node technology. FinFET and Nanosheet (NSFET) architectures [2], [3] behave similarly, and $l_{eff)}$ continues to predict the intrinsic delay for aggressively scaled MOSFETs for both device architectures, even for supply-voltages $(V_{dd})$ as low as ~0.2V, where these devices operate in the subthreshold regime. The ratio of $l_{eff}/I_{on}, I_{on}=I_{ds}(V_{ds}=V_{gs}=V_{dd})$ , as a function of $V_{dd}$ , and threshold voltage $(V_{th})$ ) show that this ratio can be significantly modulated about a typical value of ~0.5, in a manner that can be easily related to classical MOSFET behavior.

Vertically-stacked horizontal gate-all-around (GAA) Nanosheet structures have been recognized as good candidates for beyond the 7nm technology node to achieve improved power-performance and area scaling compared to FinFET technologies. Full realization of device-performance entitlement in high-performance and high-density chip designs is, therefore, of critical importance. In this paper, we present a quantitative performance evaluation of horizontal Nanosheet structures focused on key design styles as well as unique Nanosheet challenges such as gate-resistance. This analysis was performed with a fully developed design kit over a wide range of sub-7nm design, including various cell heights, as well as design features such as M1 power staples and performance-aware designs for smaller track cells.

In addition to electrostatics challenges, FinFETs scaled below CPP of 40nm will require ρC of -8×1010Ω-cm2 if performance gains are to be extended. Attainment of ρC at fully ohmic limit, and/or innovative contact structures, will be required if FinFETs are to extend performance gains below CPP of 30nm, or else a transition to a new device architecture will be required.

Recent advances in FinFET technology include fins with tapered sidewalls in addition to conventional vertical sidewall fins. Our 3-D TCAD simulation results suggest that for low to moderately doped fins, vertical sidewall fins have superior electrical performance. Only at extremely high fin doping concentrations could tapered sidewall fins be electrically beneficial.

We report that uniaxial strain in silicon FETs results in a significant modification of subthreshold and near threshold characteristics. We show that modulation of the effective mobility in the region of V-TH via uniaxial strain is very nearly proportional to that observed at high gate overdrive. Thus current-density-based V-TH should be redefined when significant mobility enhancement is achieved. In this paper, we propose a simple correction to account for strain in the definition of current-density threshold voltage. In particular, this correction may be critical in analog designs where absolute V-th are important to overdrive circuits accurately without leakage penalty.

Conventional scaling of planar CMOS devices has reached a practical electrostatic design limit at roughly 25nm gate lengths, corresponding to the 20nm node. The double-gate transistor has long been known to offer the potential to extend electrostatic scaling and in the last dozen years, workers around the world, in academia and industry, have applied a vertical fin-like embodiment of the double-gate FET, most popularly referred to as the 'FinFET,' to tackle the challenges of process, device, and product design, and accomplish the introduction of double-gate FETs into main-stream manufacturing. A view of these challenges and their solution leads to a projection that this FinFET structure will prove scalable to at least the atomic limit of CMOS scaling.

Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.

To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy use. In this work, we review circuit behavior at low voltages, specifically in the subthreshold (Vdd < Vth) regime, and suggest new strategies for energy-efficient design. We begin with a study at the device level, and we show that extreme sensitivity to the supply and threshold voltages complicates subthreshold design. The effects of this sensitivity can be minimized through simple device modifications and new device geometries. At the circuit level, we review the energy characteristics of subthreshold logic and SRAM circuits, and demonstrate that energy efficiency relies on the balance between dynamic and leakage energies, with process variability playing a key role in both energy efficiency and robustness. We continue the study of energy-efficient design by broadening our scope to the architectural level. We discuss the energy benefits of techniques such as multiple-threshold CMOS (MTCMOS) and adaptive body biasing (ABB), and we also consider the performance benefits of multiprocessor design at ultralow supply voltages.

An experimental investigation of the effects of temperature between 218K and 393K of FinFET operation in weak inversion is reported. The threshold voltage, subthreshold swing and the drain current at which extrapolated threshold voltage is defined, IVT, of fully depleted double gate n-type FinFETs are analysed. A VT temperature coefficient of -0.7mV/K is experimentally observed for our FinFETs, greater than the calculated theoretical temperature coefficient of -0.59mV/K, but smaller than that calculated for partially depleted MOSFETs (-0.9mV/K). The subthreshold swing is found to be proportional to absolute temperature, as expected. A significant dependence of IVT on temperature is observed, which raises the issue of dependence of extracted dVT/dT on extraction method

A simple and effective compact model methodology that predicts the history effect in silicon-on-insulator (SOI) is discussed. In this study we employ three physical parameters to modify the body-potentials of SOI FETs in an inverter during switching. These parameters are very challenging to measure accurately for sub-100nm devices, yet are very tightly correlated with the history effect. This methodology provides an effective means of adjusting history effects without significant alteration of the DC model. Furthermore this methodology enables construction of evaluation-level models in which DC device parametric, circuit performance and history goals exist but hardware meeting those goals is not yet available for model extraction.

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.

Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experi...

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the <100> and <100> directions showing different transport properties.

The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (TOX), voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. This work resolves seemingly contradictory observations regarding the temperature dependence of oxide breakdown. On the basis of these results, a unified, global picture of oxide breakdown is constructed, and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon-dioxide-based materials can provide a reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50-nm-technology node using silicon-dioxide-based gate insulators.

A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it is further conjectured that double-gate MOSFETs will prove to be the dominant device architecture for this last era of CMOS scaling.