DAC-based wireline transmitters are a critical component of wireline electrical links operating above 100 Gb/s. As systems explore the use of more sophisticated modulation formats such as higher-order time domain pulse amplitude modulation (e.g., PAM6 or PAM8) or frequency domain modulation (e.g., OFDM), higher linearity DACs will be required than those employed in existing PAM4 systems. This paper explores wireline DAC design. Tradeoffs between current-mode (CML) and voltage-mode (SST) drivers are described. Two design examples are presented as case studies. The first describes a CML-based 8b 56-GS/s DAC in 7nm FinFET which includes a novel integrated linearity calibration technique. The design achieves nearly 1Vppd output swing and 1.1 pJ/bit energy efficiency for 112Gb/s PAM4 signaling. The second design describes an 8b 72-GS/s DAC in 4nm FinFET with SST driver, achieving excellent static linearity to support high-order time and frequency domain modulation for future communication links.

A 0.88pJ/bit 112Gb/s PAM4 transmitter is reported in 7nm FinFET CMOS with 1V ppd output amplitude. The quarter-rate TX architecture implements a 5-tap analog FFE using tap extension circuitry, which permits higher FFE tap count than conventional quarter-rate architectures without requiring complex clocking. A key feature of the FFE construction is the use of fully re-assignable CML driver segments among FFE taps, which allows a reduced number of segments for lower capacitance and higher driver bandwidth.

This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.

A 56 GS/s 8-bit asynchronous SAR ADC fabricated in 4nm CMOS technology is demonstrated. The 16x4 interleaved ADC uses a novel bootstrapping technique and a class-AB follower in the 1 st rank interleaver. It achieves a broad input common-mode (CM) range; from 0.3V to 0.6V, the total harmonic distortion stays below -52dB at 4.1 GHz with -0.2dBFS amplitude at 0.8V PPD maximum full scale. The ADC includes analog foreground calibration means for offset, gain, skew, and bandwidth. The measured ENOB is 6.5 at low frequency and stays above 5.2 up to Nyquist frequency. The bandwidth is higher than 27 GHz. The ADC uses a single 0.8V supply voltage and achieves an efficiency of 47 fJ/conv.step.

We describe the advancements made on the automated assembly of a highly integrated 8x8 photonic switch. This switch is designed for maximum efficiency but requires proximity of optical and electrical interconnects and a well-conceived thermal solution. These constraints command innovative packaging approaches. A "fiber-last" assembly process was selected, which leverages a flip-chip joining solution to preserve the sensitive optical interfaces of the photonic circuit. A multi-fiber attach process relying on fiber self-alignment in V-grooves is used for the optical interface through which the high-speed signals are routed. It is also demonstrated that a performant optical switch engine can be constructed using standard low-cost electronic assembly principles.

We demonstrate a fully-packaged digitally programmable 8x8 strictly nonblocking electrooptic silicon photonics switch module. We measured fiber-to-fiber loss between 7.5 and 10.5 dB, crosstalk < -30 dB, and reconfiguration time < 10 ns.

This work presents the first fully packaged silicon photonics 8x8 switch with monolithically integrated electrical control circuits in 90nm SOI CMOS. The switch is a strictly non-blocking network built from 2x1 and 2x2 Mach-Zehnder switches (MZSs). 180 DACs tune the MZSs and 112 ADCs measure optical power across the network for feedback control. Digital interfaces provide low-speed tuning/monitoring and high- speed switching controls. 5.6ns optical switching is achieved with thermo-optically tuned crosstalk <-33.5dB.

We report 50- and 60-Gb/s hybrid-integrated optical links in the O-band with CMOS photonic components driven by silicon-germanium ICs using optical-domain feed-forward equalization. The link includes a segmented-electrode Mach-Zehnder modulator and a Ge photodetector that provide high bandwidths and the potential for tight integration with control and monitoring electronics. The combination of these features enables the demonstration of a 60-Gb/s AC-coupled link and a 50-Gb/s DC-coupled link with bit error rates below 10 -12 without the use of forward-error correction codes. This result provides a promising path toward extending speeds in latency sensitive optical links.

We present a Mach-Zehnder-based optical switch with novel electrooptic shift-and-dump phase shifters that have no residual amplitude modulation. As a result, the switch can have a very high extinction ratio with no overhead in power dissipation or insertion loss compared to standard electrooptic Mach-Zehnder switches. We fabricate the switch in an all-digital silicon photonic platform that monolithically integrates the actuation and control electronics together with the photonics. The switch demonstrates an extinction ratio >33 dB, insertion loss <1.2 dB, and nanosecond-scale transients. (C) 2019 Optical Society of America

We report on efforts to develop a high speed, low cost, low energy chip scale optical module for co-packaging on a first-level organic substrate for HPC and Data Center applications.

In the above-named work, the photograph that appeared next to the author, Herschel A. Ainspan, was not an image of this author and was published in error. No photo should have accompanied his name.

We report on efforts to develop optical and electrically packaged photonic switch modules in monolithically integrated CMOS technology and to interface these modules with an FPGA-based control plane facilitating reconfiguration in tens of nanoseconds.

We present a novel approach for achieving fine phase-tuning control of a Mach-Zehnder interferometer-based photonic switch. We demonstrate the concept in a fabricated silicon photonic switch containing dual thermo-optic phase tuners driven from identical monolithically integrated low-resolution digital-to-analog converters. The delivered resolution gains and additional power overheads of the demonstrated approach are assessed through experimental measurements. Using the approach, we show a resolution improvement of more than a factor of seven with only a 1.7% increase in power dissipation.

The ever-increasing demand for higher bandwidth continues to fuel the need for faster and more power-efficient IOs, with the next generation high-speed serial links expected to reach data rates higher than 112Gb/s using PAM-4 signaling [1–3]. While PAM-4 spectral efficiency is better than that of NRZ, it is less tolerant of residual ISI and noise. As a consequence, a driver with high bandwidth and large output amplitude is required. This paper presents a 64Gbaud PAM-4 TX with a fully reconfigurable 3-tap FFE, which achieves a power efficiency of 1.3pJ/b in PAM-4 mode and 2.7pJ/b in NRZ mode for a differential output swing of $1\mathrm{V}_{ppd}$. A feature of the FFE construction is the use of fully re-assignable FFE segments among the 3 taps, which allows a reduced number of segments for lower capacitance and higher driver bandwidth. To minimize power consumption, a quarter-rate clocking architecture is adopted with a tailless 4:1 multiplexer, which also acts as a pre-driver to a tailless CML output driver.

We present a novel approach for achieving coarse-fine control of two thermo-optic phase shifters in a dual-tuner Mach-Zehnder interferometer-based photonic switch. We demonstrate the concept in a fabricated silicon switch containing thermo-optic phase tuners driven from identical monolithically integrated low-resolution digital-to-analog converters.

We present an all-digital, fully programmable, nanosecond-scale photonic switch platform, monolithically integrating electronics for actuation, tuning, and power-monitoring alongside switching elements, resulting in a scalable, packageable solution for high-radix photonic switch fabrics. In this platform, we achieve record loss and extinction performances utilizing a 2 x 2 Mach-Zehnder switch (MZS) with 0.8 dB of loss and 28 dB extinction and a 2 x 2 nestedMZS with 1.3 dB of loss and 38 dB extinction. (c) 2019 Optical Society of America

This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock of 15 GHz at 60-Gb/s sampling speed to minimize the CDR loop latency. The RX is characterized in a vertical cavity surface emitting laser-based link recovering a 7-bit pseudo-random bit sequence bit pattern at 60 Gb/s with a JTOL corner frequency of around 80 MHz while maintaining an energy efficiency of 1.9 pJ/bit.