In this work, we demonstrate a self-aligned nanosheet carbon nanotube FET (CNFET) technology that fundamentally suppresses ambipolar leakage through localized extension doping. Doped extensions between the gate and contacts enable aggressive gate-length scaling down to 10 nm while achieving a high on-current of $1.2 \text{mA} / \mu \mathrm{m}$ and a low off-state current of $10 \text{nA} / \mu \mathrm{m}$ at $V_{\text{DS}}=-0.7 \mathrm{V}$, representing over $10 \times$ leakage reduction compared with prior CNFET reports. Systematic device comparisons reveal that highly doped extensions reduce leakage by $\sim 10 \times$ across both low and high drain bias, mitigate short-channel effects, and maintain high $I_{\max} / I_{\min}$ over more than 5 decades of gate-length scaling. Further, CNT diameter reduction from 1.4 nm to 1.1 nm increases the bandgap, yielding an additional $100 \times$ leakage reduction at $V_{\text{DS}}=-0.7 \mathrm{V}$ and SS of $95 \text{mV} / \text{dec}$.

Amorphous n-type metal oxides, such as In2O3 and Indium Gallium Zinc Oxide (IGZO), have shown promise as back-end-of-line (BEOL) compatible transistors, potentially offering a new paradigm for monolithic 3D stacking. However, a high-performance p-type counterpart remains a critical bottleneck. Tellurium suboxide (TeOx) has recently been shown to be a promising p-type semiconductor for BEOL applications. Yet, it remains to be seen if sub-10 nm TeOx films, needed for practical device applications, can be achieved with acceptable hole mobilities. Here, we report ultrathin TeOx transistors fabricated via cryogenic thermal evaporation at a substrate temperature of -80 °C. This low-temperature process suppresses crystallization and surface diffusion, yielding ultrasmooth films with root-mean-square roughness as low as 4 Å. The back-gated TeOx transistors achieve an on/off current ratio of 105 and a field-effect mobility of 2.8 cm2 V-1 s-1 at a channel thickness of 5.5 nm, retaining p-type switching behavior down to 2.4 nm. Selenium alloying further enhances the on/off current ratio by an order of magnitude while enabling bandgap tuning without compromising mobility.

This work reports a Carbon Nanotube (CNT) Nanosheet PFET with record performance ($I_{\text{MAX}}=0.9 \text{mA} / \mu \mathrm{m}$), leakage ($I_{\text{MIN}}$ of $20 \text{pA} / \mu \mathrm{m}$), and sub- $V_{\mathrm{T}}$ slope of $93 \text{mV} / \text{dec}$ at -0.5 V $V_{\text{DS.}}$ This result is attributed to a larger electronic bandgap which simultaneously suppresses leakage by $\sim 1000 \times$ and improves sub- $V_{\mathrm{T}}$ slope from 150 to $93 \text{mV} / \text{dec}$ at $V_{\text{DS}}=-0.5 \mathrm{V}$. Using planar single-CNT and network CNT FETs, we demonstrate feasibility of performance-matched NFET and PFET with larger bandgap. The future practical application of CNT electronics will be enabled by gate stack optimization and suppressed variation, for which key trends and targets are investigated by SRAM yield analysis.

We demonstrate that inserting an ultrathin (<1 nm) Al2O3 layer between an oxide-semiconductor (OS) channel and a high- kappa gate dielectric creates an interface dipole (ID) that shifts the threshold voltage ( V-T ) of OS transistors. The ID engineering process by Al2O3 layer integration raises V-T of 2% W-doped indium tungsten oxide (IWO) FETs by similar to 450 mV relative to a reference HfO2 stack, enabling normally-OFF operation with negligible degradation in mobility or subthreshold swing (SS). The V-T shift remains stable from 85 degrees C down to cryogenic temperatures. Under a worst case + 2-V positive bias stress at 85 degrees C, ID-engineered oxide-semiconductor field-effect transistors (OSFETs) exhibit a similar to 60-mV shift versus similar to 300 mV for the baseline device. The technique is effective across multiple OS channels [ In2O3 , indium-tin oxide (ITO) and indium-gallium-zinc oxide (IGZO)] and gate lengths down to similar to 50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain cell (2T-GC) arrays by similar to 5x10(4)x , establishing ID engineering as a low thermal budget knob for energy-efficient, high-density GC memories.

In this work, we address the off-state leakage current challenge, while simultaneously demonstrating high drive current per CNT, in NMOS and PMOS carbon nanotube field-effect transistors (CNFETs). Increasing the bandgap from 0.6 to 0.85 eV reduces the minimum current from 10-8 A/μm to 10-11 A/μm at VDS = -0.5 V with a channel length of 50 nm. By utilizing titanium as the contact metal and the YOx/AlN solid-state electrostatic doping technique, isoperformance NMOS and PMOS are demonstrated in large bandgap CNFETs. We examined the contact properties of large bandgap CNT FETs by measuring the contact barrier height and report the contact resistance with contact lengths scaled down to 18 nm. Projections for high-density CNT arrays indicate promising potential for using large bandgap CNTs as channel materials in high-performance and low-power applications.

We report the first direct extraction of CNT MOS interface metrics normalized to CNT length or CNT surface area using statistical impedance modeling and analysis of lateral capacitors measured between 100 and 300 K. Direct $D_{\text{it}}$ extraction from impedance is a crucial step towards high performance CNT MOSFETs and is enabled by (1) a statistical approach towards modeling of CNT impedance, (2) a capacitor architecture meeting the requirements for $D_{\text{it}}$ extraction, and (3) the extension of impedance acquisition to below 1 $\text{fF}$. A rigorous model treatment of surface potential fluctuations $\Delta\psi_{\mathrm{s}}$ in depletion due to fixed charge and CNT diameter variations allows to reproduce C-V features, to elucidate the physics, and to reconcile SS obtained from I-V curves with impedance data by extending the standard SS equation. CNT midgap $D_{\text{it}}$ normalized to CNT surface area of $\cong 7\times 10^{12}\text{cm}^{-2}\text{eV}^{-1}$ and increasing towards the band edge to above $5\times 10^{13}\text{cm}^{-2}\text{eV}^{-\mathrm{I}},\psi_{\mathrm{S}}$ standard deviation $\sigma_{\mathrm{s}}\cong 2.5\text{kT}$, and a midgap capture length of 0.01 nm are extracted. Preliminary process optimizations demonstrate a positive impact on the $D_{\text{it}}$ vs $E$ curve.

Abstract Semiconducting single‐walled carbon nanotube (CNT) is a promising candidate as a channel material for advanced logic transistors, attributed to the ultra‐thin 1‐nm cylindrical geometry, high mobility, and high carrier injection velocity. However, the presence of undesired CNT bundles in the CNT arrays for wafer‐scale device fabrication, even when utilizing the state‐of‐the‐art dimension‐limited self‐alignment (DLSA) method, poses challenges. These CNT bundles degrade the transistor gate's efficiency in controlling the flow of charge carriers in the CNT channel, leading to pronounced device‐to‐device variability. Here, a novel method is introduced to alleviate bundling in CNT arrays assembled via DLSA, by involving small molecule additive to screen the attractive van der Waals force between neighboring CNTs during the DLSA process, resulting in over 50% reduction in CNT bundling. Furthermore, a pioneering methodology for quantifying CNT bundles is presented and employed experimentally to assess bundles in dense CNT arrays assembled by DLSA using transmission electron microscopy. Both experimental data and molecular dynamics simulation reveal that CNT bundling originates from van der Waals attraction between CNTs, and the disturbed liquid‐liquid interface by accumulating excess polar molecules. These findings illuminate new pathways for realizing dense, bundle‐free CNT arrays.

Amorphous oxide semiconductor field-effect transistors (AOSFETs) exemplify the tradeoff between mobility, stability, and threshold voltage $(\mathrm{V}_{\text{TH}})$. In this work, a new 5-axes AOSFET evaluation framework for backend-of-line (BEOL) integration is proposed, including (i) $\mathrm{I}_{\mathrm{D}}$ extracted at a fixed over-drive beyond $\mathrm{V}_{\text{TH}}$ at 1 pA/um for performance, (ii) $\mathrm{I}_{\text{OFF}}$, (iii) $\mathrm{V}_{\text{TH}}$, (iv) subthreshold slope (SS) at 1V $\mathrm{V}_{\text{DS}}$ for off-state behaviors, and (v) $\mathrm{V}_{\text{TH}}$ shift under positive bias stress for stability. To break the tradeoff between mobility and $\mathrm{V}_{\text{TH}}$, an oxide capping layer and post-capping anneal are used on back-gated W-doped $\text{In}_{2}\mathrm{O}_{3}$ (IWO) FETs. The oxide capping and anneal demonstrate stoichiometry-independent positive $\mathrm{V}_{\text{TH}}$ shift on 1% and 2% IWO channel FETs by 0.85V and 0.4V, respectively, while mobility increases from 18.5 to 26 $\text{cm}^{2}\mathrm{V}^{-1}\mathrm{s}^{-1}$ for 1% IWO. The contact resistance is also lowered from 2185 $\Omega-\mu \mathrm{m}$ to 967 $\Omega-\mu \mathrm{m}$, enabling $\mathrm{I}_{\text{ON}}$ increase by $1.42\times$. With the oxide capping and anneal, the stability under positive bias stress improves by 300 mV to -67 $\text{mV V}_{\text{TH}}$ shift. An enhancement-mode 1% IWO FET is shown at 55 nm $\mathrm{L}_{\text{CH}}$ with positive $\mathrm{V}_{\text{TH}}=0.53\mathrm{V}$, low $\mathrm{I}_{\text{OFF}}=160\ \text{pA}/\mu \mathrm{m}, \mathrm{I}_{\mathrm{D}}=192\ \mu \mathrm{A}/\mu \mathrm{m}$ at 1E13 cm−2 charge density, and $\mathrm{I}_{\mathrm{D}}=50\mu \mathrm{A}/\mu \mathrm{m}$ extracted at a fixed over-drive voltage beyond 1 pA/um at 1V $\mathrm{V}_{\text{DS}}$.

Carbon nanotubes (CNTs) show great promise as channel material for future highly scaled transistors due to their atomic-thin body, high carrier mobility, and high injection velocity for both electrons and holes. In this work, we achieve ID greater than $300\mu \mathrm{A}/\mu \mathrm{m}$ at +/-1V VDS (iso-performance) for both N-type and P-type MOSFETs with 100nm gate length (LG) on densely aligned CNT array by self-aligned extension doping with a barrier booster [1]. Our process only modifies the extension dopant and contact metal to alter the device polarity while maintaining iso-performance. We also present the first experimental validation of tunable doping strength, mobility loss minimization, and leakage reduction capabilities of the barrier booster method, studied for top-gate CNT N-type MOSFET in this paper. Using this method, we achieve the best performance to date for N-type MOSFET on densely aligned CNT array, with $\mathrm{I}_{\mathrm{D}} > 200\mu \mathrm{A}/\mu \mathrm{m}$ and $\mathrm{I}_{\max}/\mathrm{I}_{\min}$ exceeding 104 simultaneously at 1V VDS and 500nm LG. With future improvements to the dielectric interface quality and device scaling, the benefits of CNT CMOS technology may be fully realized.

Recently a number of breakthroughs have been reported by our team in the component qualities of transistors built on Carbon Nanotube (CNT) channels. However, any emerging channel material which seeks to outperform established semiconductors for transistor logic applications has a substantial hill to climb, given the incredible capabilities of advanced Si-based logic technology platforms. This talk will first aim to frame our progress on Carbon Nanotube CMOS technology in the broader context of the value proposition and desired component qualities needed to realize practical impact in computing applications. Next, we will share advances in the fundamental building blocks for Carbon Nanotube transistors towards these targets including channel, contact, doping, and gate-stack modules. Finally we will describe new record CNT MOSFET performance milestones achieved by integrating best available device components for first time, which gives insight into the remaining performance limiters and future directions. [1] G. Pitner, et al., "Building High Performance Transistors on Carbon Nanotube Channel," VLSI 2023. [2] S. Li, et al., "High-Performance and Low Parasitic Capacitance CNT MOSFET: 1.2 mA/um at Vds of 0.75 V by self-aligned doping in sub-20 nm spacer," IEDM 2023. [3] N. Safron, et al., "Low N-type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping," IEDM 2023. [4] H.-Y. Chiu, et al., "Self-Aligned Contact Doping for Performance Enhancement of Low-Leakage Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023. [5] T.A. Chao, et al., "Small Molecule Additives to Suppress Bundling in Dimensional-Liminted Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023. [6] Q. Lin, et al., " Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors," ACS Nano 2023. [7] Z. Zhang, et al., "Complementary Carbon Nanotube Metal-Oxide-Semicondcutor Field-Effect Transistors with Localized Solid-State Extension DOping," Nature Electronics, 2023. [8] S.K. Su, et al., " Perspective on Low-Dimensional Channel Materials for Extremely Scaled CMOS," VLSI 2022. [9] Z. Zhang, et al., "Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth," ACS Applied aterials & Interfaces, 2022. [10] G. Pitner, et al., "Sub-0.5 nm Interfacial Dielectrics Enables Superior Electrostatics: 65 mV/dec top-gated Carbon Nanotube FETs at 15 nm gate length," IEDM 2020.

Carbon nanotube FETs show great promise for beyond-Si and monolithic 3D electronics, however there are still fundamental questions to explore. In particular, controlled N- and P- doping is a fundamental process module which can be used to engineer semiconductor resistance in un-gated regions such as the contact or extension, as well as optimize band-to-band tunneling leakage [1-4]. To-date both N- and P- doping has been demonstrated for CNT, but the optimal strategies for doping control and carrier density quantification have not been determined. In this work, we present a study of N- and P- doping using solid-state dopants and doping control strategy using a dielectric barrier of tunable thickness. A TCAD evaluation reveals the tradeoffs between carrier density and mobility for increasing dielectric barrier thickness, and reveals the critical role of dielectric constant in optimizing performance of spacer doping [5]. Multiple characterization approaches under evaluation help to correlate doping strength to experimentally measurable quantities with insight into the doping mechanisms. Finally, we will summarize potential approaches for improving doping control and quantification, and progress towards integration of the doping in highly-scaled high-performance carbon nanotube FETs [6]. [1] Z. Zhang, et al., “Complementary carbon nanotube metal-oxide-semiconductor field-effect transistors with localized solid-state extension doping,” Nature Electronics, 2023. [2] Q. Lin, et al., “Band-to-band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors,” ACS Nano, 2023. [3] G. Zeevi, et al., “PN Junction and band to band tunneling in carbon nanotube transistors at room temperature,” Nanotechnology, 2021. [4] L. Liyanage, et al., “VLSI-compatible carbon nanotube doping technique with low work-function metal oxides,” Nano Letters, 2014. [5] C. Gilardi et al., “Barrier Booster for Remote Extension Doping and its DTCO for 1D & 2D FETs”, IEDM 2023 [6] S.Li, et al., “High-performance and low parasitic capacitance CNT MOSFET: 1.2 mA/μm at VDS of 0.75 V by self-aligned doping in sub-20 nm spacer,” IEDM 2023.

This work demonstrates the first nanosheet FET built on an array of dense aligned carbon nanotubes. In this device structure, the gate surrounds an aligned array of CNTs with $\approx 300\text{CNT}/\mu \mathrm{m}$ . At a channel length of 70 nm the drive current exceeds $1 \text{mA}/\mu \mathrm{m}$ at -0.5 V $\mathrm{V}_{\text{DS}}$ with sub- $\mathrm{V}_{\mathrm{T}}$ slope of 135 mV/dec, and an IMIN of $76 \text{nA}/\mu \mathrm{m}. \mathrm{R}_{\mathrm{C}}$ of $20.5 \Omega-\mu\mathrm{m}$ is extracted by transmission line method. This is record-high performance for transistors with CNT channel. However, reducing $\mathrm{D}_{\mathrm{I}\mathrm{T}}$ and channel variability are necessary to enable energy-efficient CMOS applications.

Electrostatic catalysis uses an external electric field (EEF) to rearrange the charge distribution to boost reaction rates and selectively produce certain reaction products in small-molecule reactions (e.g., Diels-Alder addition), requiring a 10 MV/cm field aligned with the reaction axis. Such a large and oriented EEF is challenging for large-scale implementation or material growth with multiple reaction axes or steps. Here, we demonstrate that the energy band at the tip of an individual single-walled carbon nanotube (SWCNT) can be spontaneously shifted in a high-permittivity growth environment, with its other end in contact with a low-work-function electrode (e.g., hafnium carbide). By adjusting the Fermi level at a point where there is a substantial disparity in the density of states (DOS) between semiconducting (s-) and metallic (m-) SWCNTs, we achieve effective electrostatic catalysis for 99.92% purity s-SWCNT growth with a narrow diameter distribution (0.95 ± 0.04 nm), targeting the requirement of advanced SWCNT-based electronics for future computing.

Abstract Carbon nanotube (CNT) field effect transistors (CNFETs) show promise for the next generation VLSI systems due to their excellent scalability, energy efficiency, and speed. However, high leakage current is a drawback of large diameter CNTs (diameter (DCNT) ≥ 1.4 nm) due to the small electronic band gap (EG) ≤ 0.6 eV and effective mass. This work investigates the on‐current and off‐current tradeoff for two populations of semiconducting‐enriched CNT with DCNT ≈ 1.0 nm displaying a simultaneous 50x improvement in minimun current (IMIN) with 2.5x degradation in contact resistance compared to DCNT ≈ 1.4 nm using a Pd side‐bonded contact. A method to enhance the performance of low‐leakage CNFETs is demonstrated using sub‐monolayer self‐aligned contact doping with 0.8 nm of MoOX, which delivers a 57% reduction in contact resistance to DCNT ≈ 1.0 nm. Robustness is verified after annealing at 200 °C for 30 min and monitoring stability across 6 months post‐fabrication with no change in electrical behaviors.

Oscillatory devices have recently attracted significant interest as key components of computing systems based on biomimetic neuronal spiking. An understanding of the time scales underlying the spiking is essential for engineering fast, controllable, low-energy devices. However, we find that the intrinsic dynamics of these devices is difficult to properly characterize, as they can be heavily influenced by the external circuitry used to measure them. Here we demonstrate these challenges using a VO2 Mott oscillator with a sub-100-nm effective size, achieved using a nanogap cut in a metallic carbon nanotube electrode. Given the nanoscale thermal volume of this device, it would be expected to exhibit rapid oscillations. However, due to external parasitics present within commonly used current sources, we see orders-of-magnitude slower dynamics. We outline methods for determining when measurements are dominated by extrinsic factors and discuss the operating conditions under which intrinsic oscillation frequencies may be observed.

High-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 k$\Omega$/CNT(20.4$\Omega-\mu$m for 250 CNT/$\mu$m) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 $\mu$A/$\mu$m at -0.7V VDS.

We present dielectric barrier booster for remote extension doping in low-dimensional materials (LDMs), e.g., ID Carbon Nanotubes (CNTs) and 2D MoS 2 . In contrast to prior work, the key idea is to "engineer" the thickness of a barrier layer (t BAR ) between LDM and dopant layer, in conjunction with the dopant layer itself, to optimize various remote extension doping trade-offs (e.g., transport, leakage, doping strength, parasitic load). Understanding such trade-offs requires extensive Design-Technology Co-Optimization (DTCO), not explored in prior literature. We explore a large space of ~50,000 design points through DTCO and derive various insights, including: (a) Barrier booster is key to enabling up to 1.5× energy-delay product (EDP) benefits for CNT FET ring oscillators vs. no-barrier case, (b) Barrier booster optimization depends on the target objective function: EDP optimization favors small t BAR (to increase extension charge density) while delay optimization favors large t BAR (to improve transport properties), (c) Doping guidelines derived from DTCO are LDM-specific: for example, we project 1.9× and 4.6× EDP benefits for extension-doped (with barrier booster) CNTs and MoS 2 , respectively, vs. undoped FETs. However, if EDP-optimal parameters for MoS 2 are used for CNTs (or vice-versa), the resulting EDP benefits are <1%.

Low n-type contact resistance (R C ) of 9.7 kΩ/CNT to carbon nanotubes (CNT) with short contact length (L C ) of 20 nm is achieved by utilizing solid-state n- doping near the metal contact. AIN doping with barrier layer demonstrated in this work enables transparent electron conduction for both Pd and Ti metal contacts. We systematically explore doping strength control with barrier thickness, R C trends scaling down to 20 nm L C , CNT bandgap dependence of doping, and device stability for insight into electrical impact of key process parameters. Symmetric R C n- and p-FET reveals a clear path to meet IRDS target for 2034 device roadmap.

The performance limits of carbon nanotube field-effect transistors (CNFETs) based on a recently reported process are studied by computational techniques at temperatures between 300 K and 4 K. The impact of band-to-band tunneling (BTBT) and source-to-drain tunneling (SDT) is examined for devices with varying gate length through the use of simulations based on the non-equilibrium Green's function (NEGF) formalism, and calibrated to measurements. Additionally, the case of junctionless chemical doping profiles is analyzed in contrast to electrostatic doping recently reported for test structures. The switching limits of CNFETs are further explored for devices based on carbon nanotubes (CNTs) with more favorable electronic structures.

A semiconductor/dielectric interface is one of the dominant factors in device characteristics, and a variety of oxides with high dielectric constants and low interface trap densities have been used in carbon nanotube transistors. Given the crystal structure of nanotubes with no dangling bonds, there remains room to investigate unconventional dielectric materials. Here, we fabricate carbon nanotube transistors with boron nitride nanotubes as interfacial layers between channels and gate dielectrics, where a single semiconducting nanotube is used to focus on switching behaviors at the subthreshold regime. The subthreshold swing of 68 mV·dec −1 is obtained despite a 100-nm-thick SiO 2 dielectric, corresponding to the effective interface trap density of 5.2 × 10 11 cm −2 ·eV −1 , one order of magnitude lower than those of carbon nanotube devices without boron nitride passivation. The interfacial layers also result in the mild suppression of threshold voltage variation and hysteresis. We achieve Ohmic contacts through the selective etching of boron nitride nanotubes with XeF 2 gas, overcoming the trade-off imposed by wrapping the inner nanotubes. Negligible impacts of fluorinating carbon nanotubes on device performances are also confirmed as long as the etching is applied exclusively at source/drain regions. Our results represent an important step toward nanoelectronics that exploit the advantage of one-dimensional van der Waals heterostructures.