Variability increases with downscaling, making it a vital component in the assessment of upcoming technologies. We use a variability-aware DTCO flow, which seamlessly integrates accurate TCAD simulations with industry-proven SPICE solutions. The impact of local variability sources on SRAM KPIs is analyzed for N3 FinFET and nanosheet technologies. Assuming typical process parameters, the geometrical variations due to LWR, STI recess, and epitaxial growth significantly affect the SRAM variability. However, the main contributor to variability for N3 technologies is MGG, highlighting the crucial role of metal grains size reduction for technology optimization.

Reliability and variability-aware simulations of logic cells are essential to correctly analyze and predict the performance of upcoming technologies. A simulation flow for DTCO is presented here, which combines the accuracy of TCAD with the performance of SPICE - utilizing parasitic extractions, the impedance field method for variations, and the compact-physics simulator Comphy for reliability. Good agreement with experimental RO performance of iN14 is demonstrated and projections to N3 FinFET and nanosheet technologies are made.

We are the first to present a subband-BTE solver with a fully integrated source/drain-tunneling current calculation based on the WKB-approximation. The method is validated against ballistic NEGF calculations showing good agreement. An investigation of Si and Ge-based NWFETs is performed showing that intra-band source/drain-tunneling is not a concern for Si devices. For Ge-based PMOS devices however, tunneling leakage limits sensible L G -scaling to around 20 nm.

We present the first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells. The flow consists of parametric cell layout templates, layout-based structure generation, mixed-mode transient electrical device simulation, and data collection and analysis. Based on electrical and structural characterizations of the iNt4,iN10, and iN7 nodes, the models presented in this work feature a projection for 5 nm technology nodes based on FinFET, nanowire, and nanosheet. Transient five-stage ring-oscillator simulations show a clear advantage for the FinFET in terms of switching frequency and power consumption.

We present the first truly full-band approach to solving the subband Boltzmann transport (SBTE) equation in three-dimensional phase space. The solution is applied to investigate the evolution of the FDSOI MOSFET towards the 7nm node. Our findings show that single-gate FDSOI technology can be effectively scaled down to the 14 nm node, because the on-current gains are large enough to offset the SS-degradation. Beyond 14 nm a double-gate thin-body geometry is required to maintain electrostatic control.

We present a case study which shows the path towards design-technology co-optimization (DTCO) based on physical device modeling as opposed to simulation based on empirical mobility models. This allows for more accurate and robust predictions of device performance, and allows to assess novel process options found in 7 nm and 5 nm technology nodes. A more than ten-fold increase in computational efficiency brings turn-around times down sufficiently to make physical models suitable for the DTCO process.

Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.