This paper investigates the characterization of charge trapping and its modelling on hafnia-based ferroelectric field effect transistors (FeFETs). Defect characterization on MOSFETs can be done by studying threshold voltage shifts (∆V th ) as a function of charging and relaxation times. At positive gate voltages one expects electron trapping in the gate oxide to result in a positive shift of the threshold voltage (V th ). However, on a FeFET those conditions will induce polarization changes in the gate oxide leading to a negative V th -shift, complicating the characterization of defect levels. We aim to alleviate these difficulties by modelling the polarization and trapping in FeFETs over a wide range of timescales, suitable for defect characterization. We demonstrate quantitative agreement on long timescales with a static polarization model, while a time-dependent polarization model can be used for qualitative agreement over a wide range of times from 30 ms to 2 ks.

We demonstrate a low temperature $(\mathrm{T}\leq\mathbf{2 8 0}0^{\circ}\mathrm{C})$ atomic oxygen (O*) treatment to suppress the electron trap density in $\mathbf{H f O}_{2}$ and improve PBTI in RMG stacks, matching the reliability of a standard high thermal budget flow. This novel high-k treatment is combined with our previously demonstrated low-T atomic hydrogen (H*) treatment of the chemOx IL for NBTI improvement, thus providing a complete BTI solution compatible with Sequential 3D integration and tightly spaced nanosheet stacks (e.g., CFET). For multi- V th offerings, we deploy the low-T treatments with different Work Function Metal (WFM) stacks and observe a systematic correlation between effective WVF (eWF) and reliability, with low eWF beneficial for PBTI and detrimental for NBTI. Through Comphy simulations we show that these distinct correlations, together with the gate leakage increase at low eWF, are readily explained by assuming positive charge formation at the channel interface as the mechanism for eWF lowering in TiN/TiAl stacks with scaled TiN bottom layer. Finally, we discuss the EOT scalability of the low-T gate stacks with H * and O * treatments.

Reliability and variability-aware simulations of logic cells are essential to correctly analyze and predict the performance of upcoming technologies. A simulation flow for DTCO is presented here, which combines the accuracy of TCAD with the performance of SPICE - utilizing parasitic extractions, the impedance field method for variations, and the compact-physics simulator Comphy for reliability. Good agreement with experimental RO performance of iN14 is demonstrated and projections to N3 FinFET and nanosheet technologies are made.

We discuss low thermal budget gate stack solutions for BTI reliability, compatible with novel stacked device integration schemes (e.g., Sequential 3D) and architectures (e.g., nanosheets, CFETs). Dipole formation at the interface between the SiO2 IL and the high-k dielectric improves the nMOS PBTI reliability and enables effective Work Function tuning with a single gate metal, without any sizable impact on the EOT and physical thickness of the gate stack. For pMOS, low temperature exposure of the SiO2 IL to atomic hydrogen before HKMG deposition is shown to largely improve NBTI reliability, outmatching conventional RMG solutions based on high temperature ‘reliability anneals’ or high-k first integration.

NBTI remains a primary reliability concern for CMOS technology. Contrary to PBTI, which has been continuously reduced in the last five HKMG technology nodes, NBTI has remained virtually unchanged [1] , and is often considered an ineradicable issue. In RMG integration flows, a high-temperature (T~900°C) post-metal anneal is customary to suppress dielectric defectivity. This high thermal budget step is incompatible with novel stacked integration schemes, such as Sequential 3D and CFETs [2] . Furthermore, the so-called ‘reliability anneal’ typically requires a thick sacrificial TiN/a-Si gate, which may become unsuitable for nanosheets with tight vertical spacing. In [3] hydrogen radicals (H*) generated in a low-T remote plasma were used to passivate hole traps associated with the hydroxyl- E ’ (Η- E ’) SiO 2 defects in 1.2nm thick interface layers (IL). These defects form at stretched Si-O bonds and are abundant in IL’s grown at reduced T due to unrelaxed interface strain, causing poor NBTI reliability [3] . In this work, we i) explore the H* treatment process window , ii) optimize the treatment for ultra-thin 0.6nm chemical oxide IL’s (chemOx), focusing on EOT control, and iii) show the applicability for 1.8nm thick IL’s, of relevance for I/O devices.

We study the impact of the gate-dielectric on the Positive Bias Temperature Instability (PBTI) of IGZO thin-film transistors (TFT). We show that PBTI is controlled by the gate-dielectric pre-existent electron traps and its hydrogen content. The degradation process can be composed of up to four different mechanisms with different time kinetics, voltage acceleration factors and activation energies. A simplified physics-based model is used to reproduce stress and relaxation traces recorded in a wide range of test conditions. Gate-dielectric optimization enables scaled EOT (2.5nm) IGZO TFT to achieve a record lifetime of ~ 1 year continuous operation at 95°C and $\mathrm{V}_{\text{ov}}=1\mathrm{V}$ , with a strict failure criterion of $\vert \Delta \mathrm{V}_{\text{th}}\vert < 30\text{mV}$ .

Fabrication of stacked CMOS tiers in a 3D sequential integration requires development of low thermal budget process modules. High-quality SiO 2 interfacial layer (IL), obtained up to now only by high-temperature (≥850 °C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL's grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E' defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO 2 defects at low temperatures (100-300 °C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO 2 quality and reliability surpassing a 900 °C oxide.

CMOS technology has always exploited the high thermal stability of Si, which enables high temperature fabrication steps for various device improvements, in particular, for curing oxide defects and hence improving the device stability and reliability. However, with the rise of novel device and architecture concepts such as sequential 3D stacking of Si CMOS tiers in a monolithic integration flow, or the introduction of high-mobility Ge/III–V channels, this paradigm cannot be maintained, and the entire fabrication flow will have to be enabled at a reduced thermal budget. We investigate the current industry standard high-k dielectric, HfO2, showing how its charge trapping behavior evolves when reducing the overall fabrication thermal budget, affecting the positive bias temperature instability (PBTI) of the device. We perform this study focusing on thermal budget ranges of relevance for gate stack development compatible with future technologies. Our finding of reduced reliability at lower thermal budgets (especially <300 °C) is explained in terms of changes in the oxide defect bands, as suggested by physics-based charge trapping modeling. Our results support the hypothesis of multiple microscopic defects contributing to PBTI in HfO2: for low fabrication thermal budgets, the stretched Hf–O–Hf bonds might dominate the charge trapping kinetics, while with post-deposition anneal at temperatures >400 °C, oxygen vacancies might become the dominant species.

Electronics operating at cryogenic temperatures is crucial for scaling up single qubits to complex quantum computing systems. There are various studies concentrating on the characterization of advanced CMOS technologies operating at low temperatures, but so far little attention has been paid to reliability issues. Even though classical models predict BTI to freeze out, our measurements clearly reveal a significant threshold voltage degradation down to 4 K. This effect can be consistently explained by considering a quantum mechanical extension for the description of charge transitions in the transistor, which leads to an effective barrier lowering towards cryogenic temperatures. We implement this model in our reliability simulator Comphy and are finally able to fully explain BTI behaviour at temperatures down to 4 K.

Monolayer-thin WS2 with (0002) texture grows by chemical vapor deposition (CVD) from gas-phase precursors WF6 and H2S at a deposition temperature of 450 °C on 300 mm Si wafers covered with an amorphous Al2O3 starting surface. We investigate the growth and nucleation mechanism during the CVD process by analyzing the morphology of the WS2 crystals. The CVD process consists of two distinct growth regimes. During (i) the initial growth regime, a fast and self-limiting reaction of the CVD precursors with the Al2O3 starting surface forms predominantly monolayer-thin WS2 crystals and AlF3 crystals that completely cover the starting surface. During (ii) the steady-state growth regime, a much slower, anisotropic reaction on the bottom, first WS2 layer proceeds with the next WS2 layer growing preferentially in the lateral dimensions. We propose that the precursor adsorption reaction rate strongly diminishes when the precursors have no more access to the Al2O3 surface as soon as the WS2 layer completely covers the Al2O3 surface and that the WS2 crystal basal planes and AlF3 crystals have a low reactivity for WF6 adsorption at 450 °C. Nonetheless, a second layer of WS2 starts to form before the first WS2 layer completely covers the starting surface, albeit the surface coverage of the second layer is low (<20%, after 25 min of CVD reaction). During the steady-state growth regime, predominantly the WS2 crystals in the second monolayer continue to grow in lateral dimensions up to ∼40 nm. These crystals reach larger lateral dimensions compared to the crystals in the bottom, first layer due to low reactivity for WF6 adsorption on the WS2 basal plane compared to Al2O3. Presumably, they grow laterally by precursor species that adsorb on and diffuse across the WS2 surface, before being incorporated at the more reactive edges of the WS2 crystals in the second layer. Such a process proceeds slowly with only up to 40% surface coverage of the second WS2 layer after 150 min of CVD reaction. The CVD reaction is mediated by the starting surface: WF6 precursor preferentially adsorbs on Al2O3, whereas adsorption is not observed on SiO2. Nevertheless, WS2 grows on SiO2 in close proximity to Al2O3 in 90 nm pitch Al2O3/SiO2 line patterns. Hence, functionalization of the starting surface (e.g., SiO2 with Al2O3) can provide opportunities to grow monolayer-thin WS2 crystals at predetermined locations by selective, lateral growth with tunable crystal size, even at low deposition temperatures.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate interface dipole engineering to suppress the carrier-defect interaction and achieve sufficient nMOS PBTI and pMOS NBTI reliability without the customary post-deposition anneals.