Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as a solution. However, anomalous I-D,I-lin saturation has been experimentally observed in such devices, raising questions about its physical origin. In this work, we investigate the transport physics in ultra-scaled nanosheet FETs by solving the Subband Boltzmann Transport Equation. The simulation results reveal that secondary barriers formed in underdoped S/D extensions enhance quasi-ballistic transport even in the linear regime, providing a consistent explanation for the observed I-D,I-lin saturation in underlap devices. These insights offer guidance for optimizing S/D underlap doping profiles, highlighting the need to avoid excessive Gate-S/D overlap capacitance while preventing on-current degradation.

Contacted-poly-pitch (CPP) scalability of gate-all-around (GAA) nanosheet (NS) device is investigated in detail. Combination of NS thickness (TNS) and junction abruptness (delta) allow for spacer thickness (T-SP) and gate-length (L-G) scaling. Contact-length L-CNT scaling does not affect intrinsic performance, but scaling is limited by middle-of-line and interface resistivity. Using an extensively calibrated advanced transport model combined with the transistor design-technology co-optimization (DTCO) flow we account for accurate device and circuit intrinsics and parasitics. We highlight the trade-off between T-SP and L-G scaling whereby L-G can be scaled more aggressively if T-SP can be relaxed. T-NS can be scaled to-3.5 nm maintaining iso-performance allowing for a minimum CPP of-38 nm at L-G 10 nm. Aggressively improving delta- can further allow CPP scaling to-34 nm (L-G similar to 6 nm), though T-NS scaling gain saturates due to severe transport degradation.

Contact-poly-pitch (CPP) scalability of Gate-All-Around-nanosheet (GAA-NS) device is investigated in detail in combination with sheet thickness (${T}_{\text{ns}}$) and junction abruptness ($\delta$) both allowing for spacer-thickness ($\mathbf{T}_{\mathbf{S P}}$) and gate-length ($\mathbf{L}_{\mathbf{G}}$) scaling. Using an extensively calibrated advanced transport model combining with the DTCO flow we account for accurate device and circuit intrinsics and parasitics. We highlight trade-off between Tsp and Lg scaling (Lg scaling better than Tsp); TNs can be scaled to $\boldsymbol{\sim} \mathbf{3. 5 n m}$ maintaining iso-performance allowing for a minimum CPP of $\sim 38 ~\text{nm}\left(L_{G} \sim 10 ~\text{nm}\right)$. Aggressively improving $\delta$ can further scale CPP to $\sim 34 ~\text{nm}\left(~{L}_{{G}} \sim 6 ~\text{nm}\right)$, though $\mathbf{T}_{\text {NS }}$ scaling gain saturates due to severe mobility degradation.

Thin-film transistors based on amorphous oxide semiconductors (AOS) are promising candidates for enabling further DRAM scaling and 3D integration, which are critical for advanced computing. Despite extensive research, the charge transport mechanism in these disordered semiconductors remains poorly understood. In this work, we investigate charge transport in the archetypical AOS material, indium gallium zinc oxide (IGZO), across a range of compositions and temperatures using thin-film transistors and Hall bar structures. Our results show that the electrons involved in transport exhibit partially spatial coherence and non-degenerate conduction. Under these conditions, transport is dominated by electron transfer across insulating gaps between locally coherent regions, rather than by degenerate percolative transport above a mobility edge, or by localized-state hopping, both of which are widely assumed in the literature. While fluctuation-induced tunnelling has previously been invoked to describe low-temperature transport in oxide transistors, we show that such behavior originates from partially coherent electronic states and develop a field-effect-aware fluctuation-induced tunnelling (FEAFIT) framework that explicitly accounts for gate modulation of the tunneling landscape. The FEAFIT model accurately predicts experimental data across all compositions, temperatures, and gate voltages, enabling extraction of fundamental transport parameters. These tunnelling parameters are then correlated with electron coherence dimensions and the degree of energetic disorder obtained from first-principles calculations. Our findings advance the fundamental understanding of charge transport in AOS-based transistors and provide a foundation for further performance improvements

Amorphous indium gallium zinc oxide (a-IGZO) is becoming an increasingly important technological material. Transport in this material is conceptualized as the heavy disorder of the material causing a conduction or mobility band-edge that randomly varies and undulates in space across the entire system. Thus, transport is envisioned as being dominated by percolation physics as carriers traverse this varying band-edge landscape of “hills” and “valleys”. It is then something of a missed opportunity to model such a system using only a compact approach—despite this being the primary focus of the existing literature—as such a system can easily be faithfully reproduced as a true microscopic TCAD model with a real physically varying potential. Thus, in this work, we develop such a “microscopic” TCAD model of a-IGZO and detail a number of key aspects of its implementation. We then demonstrate that it can accurately reproduce experimental results and consider the issue of the addition of non-conducting band-tail states in a numerically efficient manner. Finally, two short studies of 3D effects are undertaken to illustrate the utility of the model: specifically, the cases of variation effects as a function of device size and as a function of surface roughness scattering.

Ferroelectric memory devices have seen intense interest over the last decade. However, in heavily scaled devices such as silicon-on-insulator (SOI), FinFETs, and nanowire-based FETs the observed ferroelectric memory window (MW) is heavily degraded owing to the fact that additional majority carriers cannot be sourced as there is no "bulk." Thus, the device never enters accumulation and polarization switching is suppressed due to the semiconductor channel remaining depleted. Here, we promote an ambipolar Schottky-based ferroelectric transistor (AS-FeFET) as an alternative design. We demonstrate that such devices-owing to their ambipolar nature and thus the ability to source both types of carriers-exhibit MWs that are consistently $\sim$ 40%-60% larger than conventional devices for the same programming conditions. Although these devices do suffer from a reduced ON-current, this tradeoff remains very attractive for many applications.

We present TCAD-based methodologies that go beyond process and device simulations of single transistors. We show that TCAD solvers can be used as effective tools to resolve the intricacies of current and future technology nodes that are otherwise difficult to access using EDA-level methods alone.

Design-Technology Co-Optimization (DTCO) emerged as pivotal driver in shaping the state-of-the-art nodes and will gain evermore importance for future technologies. This becomes most evident with the advent of complementary FETs (CFET), a technology which thrives on intricately engineered design and technology to achieve substantial boosts for both logic and memory applications. Practical DTCO implementations are realized by combination of TCAD and SPICE to achieve studies with quick turnaround times (TAT) and for seamless integration with the standard EDA design flow. Here, such a TCAD-to-SPICE DTCO flow is outlined and its application for reliability and variability-aware SRAM and RO is demonstrated.

We present a hierarchical flow for predictive TCAD device simulation in DCTO applications. Using a thoroughly cal-ibrated sub-band Boltzmann transport equation (SBTE) solver, TCAD device simulation parameters for the technology under investigation are generated automatically. This flow enables predictive accuracy of the SBTE solver at turn-around-times of SPICE simulations. It is demonstrated here for an A14 nanosheet technology, i) showing all intermediate calibration details and ii) highlighting a considerable improvement in the accuracy of ring-oscillator performance.

Memories based on a VNAND structure - whether ferroelectric or charge-trap-based - often suffer from performance issues related to the generally poor quality of their polycrystalline silicon (poly Si) channels. In-Ga-Zn-O (IGZO) has been suggested as an alternative material due to its proven history in thin-film applications. In this work TCAD models are developed that model the variability of polycrystalline silicon, amorphous IGZO and polycrystalline ferroelectric HfZrO2 (HZO) thin layers. All models are validated against experimental results and a complete parameter set for the variability models is given. The models are then used to assess the impact of selecting an IGZO-based device over a poly-Si device on the performance of a ferroelectric bit cell.

In this work a TCAD model of a ferroelectric VNAND device is developed and validated against experimental data. After its accuracy is demonstrated it is then used to explore a number of issues related to the future potential of such devices including: the expected performance if negative trapping effects are reduced, the variability issues created by the polyphasic nature of hafnium-based ferroelectric films, the issue of the destructive nature of the read sweep, and poor effect of ERS pulses. In addition, some mitigation strategies to combat these issues are briefly discussed.

Ferroelectric-based transistors (FeFETs) are an important emerging technology with applications both as conventional memories and in emerging computational paradigms such as in-memory, neuromorphic and edge computing. A common modeling approach in these structures is to treat the system as a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) effective circuit and use this to both qualitatively and quantitatively model device behavior. However, such approaches completely ignore three-dimensional effects. In this work TCAD is used to conduct three case studies meant to highlight common situations where a non-3D-modeling approach will lead to markedly incorrect predictions of device behavior. These three cases are: 1) channel percolation effects, 2) non-unixial ferroelectricity and 3) geometric depletion effects in SOI, Gate-All-Around (GAA) and nanowire devices. Finally, as a counter-case the observed steep-subthreshold in FeFETs has been argued to be a 3D percolation effect but here it is demonstrated that such behavior is present within an MFIS approach as well.

In this preprint we present a novel approach to solving the transport problem in semiconductors. We reformulate the drift-diffusion equations in terms of the quasi-Fermi-energies as solution variables; a drastic increase in numerical stability is achieved, which permits the simulation of devices at cryogenic temperatures as well as wide-band-gap devices using double precision arithmetic, instead of extended precision arithmetic which would otherwise be required to solve these applications using regular drift-diffusion.

We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.

Flash memory with a charge trap layer (CTL), also known as silicon-oxide-nitride-oxide-silicon (SONOS), is the most common type in production, yet there is a lack of consensus on the physical modeling of its operation. In Part I, we therefore proposed a full TCAD model based on an energy relaxation approach and showed that it captures experimentally observed memory operation. This numerical model, however, comes with considerable complexity and computational cost. In Part II, we therefore construct a semianalytical model based on similar physical assumptions, called Pheido, to be as simple as possible. We first derive the model equations based on a balance of current densities, detailing the approximations made. We then use Pheido to analyze the various regimes of an experimental incremental step pulse programming (ISPP) curve and compare it to the full TCAD model derived in Part I. Finally, we investigate the impact of material and structural cell parameters on the ISPP curve, illustrating how the Pheido model offers wide utility at low computational cost.

For the 3 nm technology node, horizontal gate-all-around nanosheet devices offer a non-disruptive process transition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3 nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both $V_{\min}$ and read delay even at smaller cell areas.

Due to the potential for technological application, there has been an explosion of interest in heavily polycrystalline ferroelectric nanofilms, such as those of doped hafnium oxide. However, the heavily polycrystalline nature of these materials invalidates conventional modeling approaches as the dynamics have been found to be: 1) nucleation-limited; 2) involve grains of ferroelectric material interspersed among grains of alternative, nonferroelectric material; and 3) the direct interaction between these grains is observed to be minimal. In this article, we consider seven separate compact or “0-D” models of such polycrystalline films. Four of these models are based on a Landau paradigm and two are based on a Monte Carlo (MC) paradigm. The seventh is the traditional Preisach model. Although all of these models have been used in the literature to model novel polycrystalline ferroelectric nanofilms, here we compare and contrast the accuracy and physical appropriateness of each model by comparing both their static and dynamic properties against experimental data. We then find that although all models except single-grain models are capable of reproducing the static properties, only the MC models replicate the long-time dynamical properties. Thus, it is demonstrated that not all models are equally valid for the accurate modeling of such films.

We developed a unified physical and statistical compact model of Bias Temperature Instability (BTI) effects on scaling technology nodes towards robust VLSI design, with an excessive amount of complex stress/recovery pattern characterization, ultralong-term aging prediction, and technology of statistical variability (TSV) analysis, realizing cycle-to-cycle/device-to-device reliability evaluations. This model is based on a 2/4-state Defect-Centric (DC) theory and verified by TCAD simulation, providing a deep insight into the properties of the defects (e.g., energy level distribution, occupancy probability etc.). By calibration to Fin-FET experiments (of down to 14 nm node), it is successfully implemented into BSIM-CMG for analysis of dynamic time evolutionary and dynamic voltage scaling. This physics-, variablity-, and tolerance-aware model has the potential to boost the design technology co-optimization (DTCO) flow of reliability in VLSI to the next generation of technology nodes.

Variability increases with downscaling, making it a vital component in the assessment of upcoming technologies. We use a variability-aware DTCO flow, which seamlessly integrates accurate TCAD simulations with industry-proven SPICE solutions. The impact of local variability sources on SRAM KPIs is analyzed for N3 FinFET and nanosheet technologies. Assuming typical process parameters, the geometrical variations due to LWR, STI recess, and epitaxial growth significantly affect the SRAM variability. However, the main contributor to variability for N3 technologies is MGG, highlighting the crucial role of metal grains size reduction for technology optimization.