This paper highlights the challenges and solutions associated with forming backside source/drain (S/D) contact with low contact resistivity (RhoC). The backside nanosecond laser anneal (NLA) process window is identified by thermal simulation and experimental verification of resistance and reliability impact on the frontside Cu-based back-end-of-line (BEOL). Optimal NLA energy dose (ED) is implemented on nanosheet transistors achieving low RhoC backside contact.

This paper examines various approaches for integrating backside power distribution network (BSPDN) with nanosheet transistor technologies. Deep Trench Via (DTV) based BSPDN schemes, except for Shifted Frontside Via Backside Power rail (SFVBP), do not offer cell level scaling benefits, but via resistance of SFVBP could remain a bottleneck. Direct Backside Contact (DBC) based schemes offer best cell level scaling. A novel self-aligned backside contact (SABC) scheme integrated with nanosheet transistors is demonstrated with immunity to misalignments in backside contact formation. The structure exhibits good device characteristics and satisfactory reliability.

Semiconductor industry transitions from the era of planar FETs to the era of three-dimensional (3D) transistors greatly improving performance per footprint. In planar FETs, the gate width W G , the lateral source/drain (S/D) size, and the metallic contact width W C are all equal to the transistor width W. FinFETs feature a 3D channel geometry where the gate perimeter W G per fin or, equivalently, the effective channel width W eff is significantly larger than the fin pitch P that defines the S/D and metallic contact width per fin (Fig. 1). Large W eff reduces the channel resistance but small P increases the parasitic external resistance R EXT making it a performance limiting factor. Innovative processes and new materials are required for reducing components of R EXT thereby realizing FinFET performance advantage. This work explores millisecond and nanosecond laser annealing techniques for reducing FinFET R EXT focusing on source/drain and contact resistances. Transistor-level specific contact resistivity in sub 10 -9 Ω-cm 2 range has been achieved for both nFETs and pFETs with corresponding improvements in R EXT and switching currents.

In order to tackle the CMOS contact resistance bottleneck, we developed a contact cavity shaping process that leverages a Reactive Ion Etching (RIE) technology, and a selective highly doped SiGe:B epitaxial process allowing an active boron doping level of 2E21 at.cm-3. By co-optimizing these processes in the contact module on 300mm wafers, we demonstrate a record low transistor contact resistance of 11 $\Omega.\mu$m of W eff with corresponding effective $\rho_{\mathrm{c}}$ of 5.2$\times 10^{-10}\Omega$.cm 2 , which translates into a device I eff performance gain of 44/19% (median/leading edge).

Positron annihilation was used to probe vacancy-type defects in electrodeposited Cu films after nanosecond pulse laser annealing. For the as-deposited Cu film, we identified the coexistence of two different vacancy-type defects, vacancy clusters (such as V16) and monovacancy-type defects, coupled with impurities. An enlargement in the vacancy size was observed after the laser annealing process. The size of these defects was estimated to be close to V30, and such defects could not be formed by conventional furnace annealing. After furnace annealing at 400 °C, the size of the larger vacancy clusters decreased, but that of the smaller vacancies increased. The observed change in the sizes of vacancies is considered to be related to interactions between vacancies and impurities. The depth profile of the defects varied by changing the laser energy density and the number of laser shots. The impact of laser annealing on the vacancy-type defects was observed even after furnace annealing at 800 °C. Because the presence of point defects in electroplated Cu directly correlates with electromigration and grain growth, the ability of laser annealing to introduce large vacancy clusters in the localized region shows the potential of nanosecond laser annealing as a low-thermal budget process tool for back-end-of-line materials.

Recent progress in materials, processes and integration schemes to reduce line resistance (Line-R) of damascene Cu and alternative conductors (damascene Co and subtractive Ru) are reviewed, including (1) graphene/Co capped Cu to achieve both EM reliability and Line-R reduction (2) nanosecond laser anneal of Ru blanket films for subtractive-etched interconnects, (3) single damascene Cu, which is potentially one way to extend Cu to extreme nodes, and (4) Co/Cu composite integration to preserve Cu power rails. Finally, the technology shift from Cu to alternative conductors is discussed from the viewpoint of Line-R crossover.

We review the crystallization of hafnium-oxide-based ferroelectrics intended for back-end-of-line (BEOL) integration. We discuss furnace, rapid thermal, and nanosecond Laser anneals of undoped and aluminum-doped HfO 2 as well as of hafnium zirconium oxide, Hf 1-x Zr x O 2 . Crystallization and phase formation during rapid anneal is characterized via temperature-dependent X-ray diffraction. We also demonstrate a ferroelectric tunnel junction formed via nanosecond Laser anneal of undoped HfO 2 .

A novel nanosecond (ns) laser anneal (multiple laser shots at sub-melting low laser energy) was employed to reduce the blanket sheet resistance of Ru thin films deposited by physical vapor deposition (PVD). The laser anneal was conducted after PVD Ru deposition and then followed up with a standard 400°C anneal in a forming gas environment. Blanket sheet R decreased by 30% for the laser + furnace annealed Ru films, whereas the drop for just 400°C furnace annealed Ru films was only 18%. Multiple laser exposures at an optimized laser fluence was identified as a key factor in enabling this benefit at BEOL compatible thermal budget suitable for scaled-down Ru interconnects.

Feasibility of single damascene Cu BEOL nanowires with TaN/Ta barrier (i.e. omitting a CVD-Co liner) was studied. Successful Cu gap-fill in 36 nm pitch trenches demonstrated 30% line resistance (Line-R) reduction vs. leading-edge Cu with conventional TaN/Co liner. This was attributed to larger Cu volume fraction and 15% lower intrinsic Cu resistivity. In order to assess the Line-R crossover point, comparable Ru nanowires were estimated through analysis of electron scattering components, based on Rs of blanket Ru films. The calculation predicts Line-R of subtractive-etched Ru lines (larger grains) crosses conventional Cu with TaN/Co liner at 12 nm linewidth, but never crosses Cu with TaN/Ta liner. Analysis of electron scattering components shows the resistivity of Ru lines will be dominated by grain boundary scattering, suggesting that the key for subtractive-etched Ru wires crossing over Cu would be innovations that enhance grain growth of blanket Ru films.

Nanosecond (NLA) laser annealing is under consideration for inclusion into mainstream CMOS technology. Lack of suitable ultra-high speed pyrometery and the complexity of determining surface temperature of patterned, nanostructured wafers poses unique challenges in tool monitoring and process setup. This work sets a methodology of calibrating the incident energy density (ED) at the wafer plane and the surface temperature for blanket and pattern wafers. The melting of undoped crystalline silicon (c-Si) at 141°C and that of the transistor channel were used as reference points for blanket and patterned wafers, respectively. Laser-induced epitaxial re-growth of amorphized layers and pockets and the melting of the pFET SiGe source/drain (S/D) were used to show consistency between the calibrated incident ED and predicted surface temperature. This methodology allows for reliable annealing process setup and adequate periodic tool monitoring and matching.

Laser Annealing was introduced into mainstream CMOS manufacturing nearly a decade ago and since then has been evolving capturing new applications and expanding into new process regimes. This invited paper provides an overview of the adoption and the applications of millisecond-scale laser annealing in CMOS technologies. Building on the presented historical perspective, this paper then discusses and compares applications of nanosecond-scale laser annealing in future CMOS technologies. Mitigation of thermal pattern effects are also discussed in the context of different device architectures built on both bulk and SOI substrates.

We report on a significant pFET external resistance reduction (∼40%) and corresponding 10% R ON decrease by nanosecond laser annealing of S/D structures applicable to advanced technology nodes. Selective melting of pFET S/D elements is responsible for this improvement. Process window boundaries are defined by channel and junction melting at the upper end and by S/D SiGe melting at the lower end. Short channel characteristics are not degraded within the identified process window. Contacted gate pitch (CPP) and fin number dependence of the process window is assessed.

Laser Annealing was introduced into mainstream CMOS manufacturing nearly a decade ago and since then has been capturing new applications and expanding into new process regimes. This talk reviews applications of millisecond-scale laser annealing in CMOS technologies from dopant activation to gate dielectric reliability effects to creating metastable alloys to forming silicides. Mitigation of thermal pattern effects and laser-induced substrate distortions are discussed in the context of different device architectures built on both bulk and SOI substrates. Nanosecond-scale laser annealing greatly expands the annealing process space enabling synthesis of highly metastable alloys, spatially selective thermal processing, and targeted thermal treatments with virtually zero impact on the overall thermal budget. Building on the presented historical perspective, we discuss and compare applications of nanosecond-scale laser annealing in future CMOS technologies with 3-dimensional transistors and advanced BEOL interconnects.

Understanding and simulating 3D doping performed by Plasma Immersion Ion Implantation on FinFETs or on deep trenches for flash memories or power devices applications is a key topic to optimize process parameters and to forecast effect of form factor evolution requested by technology scaling. In this work, we developed a model based on the following strategy. 1- Calculation of angle and energy distribution of ions and neutrals reaching wafer surface as function of PIII process parameters (TRIM Monte Carlo simulation in gases) 2- Calculation of local ion distributions (quantity, angle and energy distribution) along the top, walls and bottom of Fins or trenches based on simple geometrical model with shadowing effect. 3- Calculation of local in depth dopant distribution on all points of the structure based on TRIM Monte-Carlo simulation 4- Recalculation of mean concentration profile and comparison with 1.5D SIMS. Effect of main process parameters (plasma density and pressure) is shown as well as geometrical parameters of doped structures (aspect ratio, tapering angle). After having compared the model to experimental data, impact of geometrical changes due to technology scaling is discussed (fin pitch for Finfet application, form factor for trench doping applications)

This work thoroughly investigates the external parasitic resistance in advanced FinFET technology. The optimization of the parasitic resistance is systematically examined in terms of 1) source/drain epi resistance, 2) contact resistance and 3) middle of line metal stud resistance. Various resistance reduction knobs have been experimentally explored in these three aspects and low contact resistivity of $1\times 10^{-9}$ and $7\times 10^{-10} \Omega\cdot \text{cm}^{2}$ have been demonstrated on transistor level for NFET and PFET. By combining all the parasitic resistance reduction strategies, more than 70% and 60% reductions [1] in external parasitic resistance have been realized on NFET and PFET, respectively.

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Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as V t and gate stack, defines an upper process boundary and translates to with-in-die (WID V t variation. Combining DB laser annealing technique with process-friendly layouts enables contact resistance benefit without degrading product level variability.

In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10 −9 Q-cm 2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.

We report record low 8.4 × 10-10 Ω-cm2 n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.