This work thoroughly investigates the external parasitic resistance in advanced FinFET technology. The optimization of the parasitic resistance is systematically examined in terms of 1) source/drain epi resistance, 2) contact resistance and 3) middle of line metal stud resistance. Various resistance reduction knobs have been experimentally explored in these three aspects and low contact resistivity of $1\times 10^{-9}$ and $7\times 10^{-10} \Omega\cdot \text{cm}^{2}$ have been demonstrated on transistor level for NFET and PFET. By combining all the parasitic resistance reduction strategies, more than 70% and 60% reductions [1] in external parasitic resistance have been realized on NFET and PFET, respectively.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a ftinctional SRAM with cell size of 0.37 mu m(2), and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840 mu A/mu m and 1240 mu A/mu m respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0.

The present paper deals with the different techniques investigated in the whole microelectronics community to integrate air cavities, usually known as air gaps, in-between copper lines for advanced interconnects. The different integration processes were split into two categories, i.e. (i) using a non-conformal CVD deposition inside patterned trenches and (ii) by removing a sacrificial material using a specific technological operation. Advantages and drawbacks of the different approaches will be discussed, including integration issues, manufacturability, and electrical performances. The aim of the paper is to sensitize the BEOL community on these specific approaches that now appear attractive considering the electrical performances required for 45 nm and below technological nodes.

PVD TiZrN has been investigated as a potential barrier material for current and future copper metallization. A process was developed that provided stable film characteristics. Several techniques were used to characterize TiZrN as a barrier material. Patterned wafers showed the film provided adequate step coverage and barrier performance. Electrical measurements were made on 0.13 mum and 0.09 mum technology node dual inlaid patterned wafers. Equivalent and improved characteristics were seen as compared to the traditional Ta-based barrier.

The integration challenges of a low-k dielectric (k < 3) to form multi-level Cu interconnects for the next generation 0.1 /spl mu/m CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfront control, resist poisoning, high aspect ratio metallization, and improved CMP planarity. The maturity of this technology has been demonstrated through high yield of a 4MB SRAM test vehicle.

Metalorganic chemical vapor deposition (MOCVD) titanium silicon nitride (TiSiN) has emerged as a strong candidate for a next-generation diffusion barrier material in copper/low-k dielectric back-end-of-line (BEOL) device fabrication. As ionized physical vapor deposition (PVD) Ta(N) barriers currently used in high-volume production begin to exhibit marginal film continuity in high aspect ratio device features, more conformal barrier materials become a requirement. Material, electrical, and reliability properties are strongly influenced by CVD TiSiN film thickness, process sequencing, and incoming surface cleanliness of device features. TiSiN has been shown to possess the necessary material and electrical properties to be successfully integrated in sub-130 nm copper/low-k semiconductor device technology nodes.

Chemical Vapor Deposition (CVD) Titanium-Nitride Silicon (TiN(Si)) films were evaluated to address the current and expected limitations of physical vapor deposition (PVD) barrier and Cu seed processes on sub 130 nm node back-end-of-line (BEOL) Cu technology device fabrication. The methods and typical film responses are described from the reaction of Tetrakis (DiEthylAmido) Titanium (TDEAT) and Ammonia (NH3) with Silane (SiH4). CVD TiN(Si) films were characterized by 4-point probe for sheet resistance; XRF/XRR for thickness/deposition rate; surface particle counter for in-film defects; Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) for step coverage and Cu electrochemical plating fill; Four point bend for adhesion to various dielectrics; Atomic Force Microscopy (AFM) for surface roughness and morphology; Time-of-Flight Secondary Ion Mass Spectroscopy (TOF-SIMS) and Rutherford Backscattering (RBS) for material stoichiometry and interfacial impurities; electrical via resistance and integration responses from single inlaid BEOL integration, with low K and ultra low K dielectric materials. The results indicate that a CVD TiN(Si) Cu barrier can satisfactorily replace the cur-rent PVD barriers for sub 130 nm node device fabrication.

The paper deals with the introduction of an innovative self-aligned capping layer leading to the formation of a Cu/Si/N mixed interface. The process was first developed targeting the aggressive 65 nm technology node and below. After optimisation, the process was successfully introduced in a well known Cu/FSG integration scheme prior to SiN etch stop layer deposition; process interest and maturity was demonstrated on 300 mm wafers in a 110 nm technology node by showing both its full compatibility with industrial requirements for stabilized technology and clear performance improvements in terms of electrical performance, defectivity and resistance to electromigration. These results open large perspectives for the integration of a Si-based self-aligned barrier on Cu lines, the process capability covering several technology nodes used either in addition to thin dielectric barriers or as a single capping of the copper lines.