Functional SRAM arrays are frequently used as yield learning vehicles for semiconductor technology development [1]. However, the complexity of the peripheral circuitry in a traditional SRAM (e.g. address decoder, write driver, sense amp, IO circuits, redundancy control) may limit bitcell array access. When peripheral circuity fails, it restricts the ability to extract and analyze array bit-fail maps, thereby preventing electrical fault isolation, failure analysis, and technology yield learning. In this paper, we present an SRAM test structure called "Array-Only SRAM" (AOS) which does not utilize peripheral circuitry for use as an early technology yield learning vehicle.

We present a monolithic stacked FET architecture featuring a stepped channel structure where the bottom FET channels are wider than the top. Such a design relieves high aspect ratio process challenges by reducing the total stack height and provides better performance as compared to its uniform channel width counterpart at the same footprint. In addition to the stepped channels, our integrated hardware work features top-bottom channel middle dielectric isolation, top-bottom source/drain isolation and dual work function metals. As the advanced technologies are facing significant power, performance and area scaling pressures, this work extends the narrowing road beyond the nanosheet architecture.

Abstract In the ever-increasing complexity of today’s state-of-the-art semiconductor structures, it is desirable to seek any advantage in the fault isolation and analysis paradigm to improve time to data. This paper discusses one such improvement where it is shown to be possible to target silicon (Si) devices, their metal contacts, or any other location in the wafer stack in a SRAM test structure from metal level 7 (M7) for transmission electron microscopy (TEM) sample fabrication using a modified sample geometry, focused ion beam (FIB) software targeting tools, and planning for failure analysis at the mask design stage. Electron beam inspection data was used to drive back to the location of interest in this example. The subsequent analysis shows a silicon and oxygen rich material creating an open contact defect signature.

This paper addresses the key challenges of copper (Cu) undercut control using the end point detection (EPD) system based on the Applied Materials Raider tool. The Cu etch rate was measured with the timed etch to validate the end point detection on blanket wafers. The end point traces were then collected on C4 pillars under 0, 25, 50, and 100% over etch conditions. C4 pillars undercut amounts were measured using Focused Ion Beam Scanning Electron Microscopy (FIB-SEM). The ability to detect the endpoint (EP) and stop at a defined over etch (OE) from the end point was demonstrated. Based on FIB-SEM and Energy dispersive X-ray (EDX), we have developed an endpoint recipe with minimal undercut.

We discuss the process challenges such as the heater geometry effect, heater patterning processes and deep via formation. Based on the electrical data, we improve the processes and Phase Change memory (PCM) resistance distribution to meet Analog Computing requirement.

Analog non-volatile memory (NVM)-based accelerators for deep neural networks implement multiply-accumulate (MAC) operations – in parallel, on large arrays of resistive devices – by using Ohm’s law and Kirchhoff’s current law. By completely avoiding weight motion, such fully weight-stationary systems can offer a unique combination of low latency, high throughput, and high energy-efficiency (e.g., high TeraOPS/W). Yet since most Deep Neural Networks (DNNs) require only modest (e.g., 4-bit) precision in synaptic operations, such systems can still deliver “software-equivalent” accuracies on a wide range of models. We describe a 14-nm inference chip, comprising multiple 512×512 arrays of Phase Change Memory (PCM) devices, which can deliver software-equivalent inference accuracy for MNIST handwritten-digit recognition and recurrent LSTM benchmarks, and discuss various PCM challenges such as conductance drift and noise.

Middle of Line (MOL) metallization with cobalt has been very promising to reduce the parasitic resistance of advanced CMOS devices. Though significant line resistance reduction has been demonstrated, there are still many challenges in cobalt MOL integration especially for yield improvement. In this study, via resistance and yield are found to be related to the queue time from cobalt CMP to dielectric cap deposition. The failure analysis shows cobalt erosion causing open via resistance. Cobalt erosion is caused by moisture and residual fluorine gas in the FOUP. By using N2 purged FOUP, the via resistance yield is improved.

Vertical-transport FET (VTFET) is a strong candidate for future CMOS technology. The concept of VTFET has been demonstrated in our previous report, which enables to scale logic area beyond sub-45nm contacted gate pitch (CGP). This paper focuses on performance assessment of VTFET based on hardware (HW). 1. 2x effective capacitance $(\mathrm{C}_{\mathrm{e}\mathrm{f}\mathrm{f}})$ contrasting to technology target is demonstrated based on 40CGP VTFET ring oscillator. Two major bottlenecks are identified as DC performance $(\mathrm{I}_{\mathrm{e}\mathrm{f}\mathrm{f}}$ at target $\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$) detractor. 90% DC performance compared to the target has been demonstrated by resolving the bottlenecks.

Abstract There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

We demonstrate, for the first time, Vertical-Transport Nanosheet (VTFET) CMOS logic transistors at sub-45nm gate pitch on bulk silicon wafers. We show that VTFETs present an opportunity to break the Contacted Gate Pitch (CGP) barrier faced by Lateral-Transport FETs. VTFETs offer scaling relief for electrostatics and parasitics by decoupling key device features from CGP-scaling roadblocks. First, nMOS/pMOS VTFET electrostatics are reported at sub-45nm gate pitch with $\text{SS} = 69/68\ \text{mV}/\text{dec}$ and sub-30mV DIBL. Well-behaved short channel characteristics with Si/SiGe source and drain are demonstrated in hardware. Symmetric device characteristics for SS and DIBL are achieved (with process optimization). Vertical nanosheets are utilized rather than vertical nanowires [1], [2] for improved performance and area scaling. Functional ring oscillators demonstrate the excellent effective capacitance (Ceff) scaling advantages of VTFET nanosheets. Logic area scaling is furthered by use of Zero Diffusion Break (ZDB) isolation to eliminate dummy gates. Innovative I/O FET device design and hardware characteristics are shared.

Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary deep neural network (DNN) topologies. In this article, we present a 14-nm test-chip for Analog AI inference—it contains multiple arrays of phase change memory (PCM)-devices, each array capable of storing 512 $\times $ 512 unique DNN weights and executing massively parallel MAC operations at the location of the data. DNN excitations are transported across the chip using a duration representation on a parallel and reconfigurable 2-D mesh. To accurately transfer inference models to the chip, we describe a closed-loop tuning (CLT) algorithm that programs the four PCM conductances in each weight, achieving <3% average weight-error. A row-wise programming scheme and associated circuitry allow us to execute CLT on up to 512 weights concurrently. We show that the test chip can achieve near-software-equivalent accuracy on two different DNNs. We demonstrate tile-to-tile transport with a fully-on-chip two-layer network for MNIST (accuracy degradation ~0.6%) and show resilience to error propagation across long sequences (up to 10 000 characters) with a recurrent long short-term memory (LSTM) network, implementing off-chip activation and vector-vector operations to generate recurrent inputs used in the next on- chip MAC.

AlOx was selectively deposited on top of SiCOH in 32 nm pitch Cu-SiCOH pattern to form a Fully Aligned Via (FAV) test structure. Selective deposition process performance and its integration into the 5nm BEOL FAV structure were evaluated. The selective AlOx deposition involves multistep process including surface treatment, selective Self-Aligned Molecules (SAM) bonding to inhibit Cu metal surface, and the selective growth of AlOx on top of SiCOH dielectric using Chemical vapor deposition process with various precursors and process conditions below 300°C. Thin selective AlOx of 4–6 nm thickness show excellent selectivity on SiCOH over Co capped Cu-SiCOH patterned structures with various spacing. The Via Chain electrical yields were measured on 32 nm pitch structures by AlOx selective deposition and are comparable to the established FAV process by Cu wet recess. This indicates that the Selective AlOx deposition process is highly selective on SiCOH dielectric surface without defect formation in the Co Capped Cu surfaces.

A novel nanosecond (ns) laser anneal (multiple laser shots at sub-melting low laser energy) was employed to reduce the blanket sheet resistance of Ru thin films deposited by physical vapor deposition (PVD). The laser anneal was conducted after PVD Ru deposition and then followed up with a standard 400°C anneal in a forming gas environment. Blanket sheet R decreased by 30% for the laser + furnace annealed Ru films, whereas the drop for just 400°C furnace annealed Ru films was only 18%. Multiple laser exposures at an optimized laser fluence was identified as a key factor in enabling this benefit at BEOL compatible thermal budget suitable for scaled-down Ru interconnects.

Abstract In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge2Sb2Te5. We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.

Power consumption of conventional CMOS semiconductor architectures has grown to the point where novel structures need to be introduced to mitigate the power load within the chip. The introduction of the specialized artificial intelligence devices goes hand in hand with the inception of novel materials and processes into conventional semiconductor fabrication, which drives the need for expanding the host of failure analysis techniques and diagnostic capabilities. This paper describes a case study of elemental transmission electron microscopy tomography on an exploratory phase change memory test structure and comments upon some technique observations: advantages and disadvantages.

We present the first Embedded Spin-Transfer-Torque MRAM (eMRAM) technology in a 14 nm CMOS node. A novel integration supports the highest eMRAM density (0.0273 um2 cell size), optimal magnetic tunnel junction (MTJ) placement between M1-M2 for performance and density, and the lowest-cost integration scheme, with only 3 added mask levels (2 critical + 1 non-critical) and a single added electrode module. An advanced 400°C-compatible MTJ stack is read and written by innovative reference-cell sensing circuitry. We demonstrate digital functionality and write performance down to 4 ns, with companion parametric analysis for magnetoresistance, switching voltage, retention, and endurance cycling. Finally, we checked the 14 nm eMRAM hardware BEOL EM and TDDB at the critical levels, verifying good reliability after the embedding process.

We report that n-dipole and p-dipole (dual dipoles) can be co-integrated to provide a more flexible volumeless multiple threshold voltage(multi-Vt) solution in FinFET and Nanosheet (NS) technologies. The p-dipole process for dual dipoles co-integration is identified. When the Vt shift is less than 100m V, the mobility is slightly degraded, but other properties are not clearly affected. The improved pFET performance is from the Vt reduction. The dipole co-integration also provides a novel method for Vt definition via dipole Vt compensation. Our selective dipole enablement can implement near bandedge (BE) multi- Vt for high performance application.

Feasibility of single damascene Cu BEOL nanowires with TaN/Ta barrier (i.e. omitting a CVD-Co liner) was studied. Successful Cu gap-fill in 36 nm pitch trenches demonstrated 30% line resistance (Line-R) reduction vs. leading-edge Cu with conventional TaN/Co liner. This was attributed to larger Cu volume fraction and 15% lower intrinsic Cu resistivity. In order to assess the Line-R crossover point, comparable Ru nanowires were estimated through analysis of electron scattering components, based on Rs of blanket Ru films. The calculation predicts Line-R of subtractive-etched Ru lines (larger grains) crosses conventional Cu with TaN/Co liner at 12 nm linewidth, but never crosses Cu with TaN/Ta liner. Analysis of electron scattering components shows the resistivity of Ru lines will be dominated by grain boundary scattering, suggesting that the key for subtractive-etched Ru wires crossing over Cu would be innovations that enhance grain growth of blanket Ru films.

Ring Oscillators (ROs) are used for yield learning during the research phase of a CMO technology. We performed cross-sections and showed that the open and short defects are in the middle of line (MOL) gate structures. The defects which are related to MOL or prior processes, as well as the design and density, will be discussed in the paper.

Voids in copper lines are a common failure mechanism in the back end of line (BEOL) of integrated circuits manufacturing, affecting chip yield and reliability. As subsequent process nodes continue to shrink metal line dimensions, monitoring and control of these voids gain more and more importance [1]. Currently, there is no quantitative in-line metrology technique that allows voids to be identified and measured. This work aims to develop a new method to do so, by combining scatterometry (also referred to as Optical Critical Dimension or Optical CD) and low-energy x-ray fluorescence ( LE-XRF), as well as machine learning techniques. By combining the inputs from these tools in the form of hybrid metrology, as well as with the incorporation of machine learning methods, we create a new metric, referred to as V-xo, to characterize the quantity of void. Additionally, the results are compared with in-line electrical test data, as higher amounts of voids were expected to increase the measured resistivity. This was not found to be the case, as the impact of the voids was much less of a factor than variation in the cross-sectional area of the lines.