This paper details the device physics of Silicon Carbide MOSFETs in third quadrant operation. It is observed that the gate bias has a large effect on controlling the injection efficiency at the anode of the body diode. The change in threshold voltage due to body-effect and the voltage drop across the anode junction play a key role in controlling the balance between electron and hole currents at the anode end, which gives the device the capability to operate in unipolar, bipolar or intermediate conduction modes depending on current density and operating temperature.

The purpose of this paper is to introduce a dynamic electro-thermal simulation and analysis approach for device design and short-circuit safe-operating-area (SOA) characterization using a physics-based electro-thermal Saber®∗ model. Model parameter extraction, simulation, and validation results are given for several commercially available 4H-silicon carbide (SiC) power MOSFETs with a voltage rating of 1200 V and with current ratings of 31.6 A and 42 A. The electro-thermal model and simulations are used to analyze the short-circuit SOA including the measured failure time (tfailure) and simulated device internal junction temperature (Tj) at failure for different gate voltages (VGS) and drain voltages (VDS).

The purpose of this paper is to present a physics-based electro-thermal Saber®* model and parameter extraction sequence for high-voltage SiC buffer layer n-channel insulated gate bipolar transistors (IGBTs). This model was developed by modifying and extending the previously developed physics-based silicon buffer layer IGBT electrothermal model and IGBT Model Parameter extrACtion Tools (IMPACT) to include SiC specific device and material properties. The validated simulation results in this paper demonstrate that the new electro-thermal Saber® model for high-voltage SiC buffer layer n-channel IGBTs can be used to describe the static and dynamic behaviors for a wide range of device designs and circuit conditions for IGBTs with blocking voltages from 12 kV to 20 kV. The new physics-based model provides both device and circuit predictive capability.

The optimization of medium voltage hybrid Si IGBT/SiC junction barrier Schottky diode modules is explored. The primary variant in the study is the active device area of the SiC JBS diodes for a fixed Si IGBT area. The optimization is performed through electro-thermal circuit simulations using validated physics-based device models. Parameters tracked include device switching losses, conduction losses and junction temperature. Finally, reliability issues were considered. SiC JBS diodes were subject to surge conditions and diode surge current was evaluated during module optimization.

The latest developments in ultra high voltage 4H-SiC IGBTs are presented. A 4H-SiC P-IGBT, with a chip size of 8.4 mm x 8.4 mm and an active area of 0.32 cm2, which is double the active area of the previously reported devices [1], exhibited a blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 41 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 17 kV, and demonstrated a room temperature differential specific on-resistance of 25.6 mΩ-cm2 with a gate bias of 20 V. Field-Stop buffer layer design was used to control the charge injection from the backside. A comparison between N- and P- IGBTs, and the effects of different buffer designs, are presented.

We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm x 6.7 mm and an active area of 0.16 cm(2) exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 m Omega-cm(2) with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 m Omega-cm(2) with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.

The performance of Junction Barrier Schottky (JBS) diodes developed for medium voltage hard-switched Naval power conversion is reported. Nominally 60 A, 4.5kV rated JBS freewheeling diodes were paired with similarly rated Si IGBTs and evaluated for temperature dependent static and dynamic characteristics as well as HTRB and surge capability. The SiC JBS/Si IGBT pair was also directly compared to Si PiN diode/Si IGBT with similar ratings. Compared to Si, the SiC freewheeling diode produced over twenty times lower reverse recovery charge leading to approximately a factor-of-four-reduction in turn-on loss. Alternatively, for equivalent total switching loss, the SiC JBS/Si IGBT hybrid configuration allows for at least a 50% increase in specific switched power density. Reliability testing showed the devices to be robust with zero failures.

Transient liquid phase (TLP) bonding is an advanced die-attach technique for wide-bandgap power semiconductor and high-temperature packaging. TLP bonding advances current soldering techniques by raising the melting point to over 500 °C without detrimental high-lead materials. The bond also has greater reliability and rigidity due in part to a bonding temperature of 200 °C that drastically lowers the peak bond stresses. Furthermore, the thermal conductivity is increased 67 % while the bond thickness is substantially reduced, lowering the thermal resistance by an order of magnitude. This work provides an in-depth examination of the TLP fabrication methodology utilizing mechanical and thermal experimental characterization data along with thermal reliability results.

A software-controlled thermal cycling test system developed for SiC module package characterization is presented. The software interface permits the flexible definition of testing parameters such as variable data acquisition rates, customizable cycle transition's duration, and the independently controlled heating and cooling rates of the test. The cycle's heating is provided by a controlled power supply, while two independent mass flow controllers provide the cycle's cooling control, which can be a combination of air and water flows depending on the test conditions. The interface provides visual feedback by continuously showing the heatplate temperature and the thermal cycling measurements in situ. The system has shown to be a useful tool in a comprehensive package degradation project through the monitoring package and electrical variation due to thermal cycling.

Adequate modeling of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is dependent on accurate characterization of the inter-electrode capacitances. With the advent of high-voltage silicon carbide (SIC) power MOSFETs, it has become important to develop a measurement system that can perform and record high-voltage capacitance versus voltage measurements on these devices. This paper describes a measurement apparatus that safely and accurately allows high voltage capacitance-voltage (CV) measurements to be performed. The measurements are based on conventional LCR (Inductance (L), Capacitance (C), and Resistance (R)) meter CV techniques but with added circuitry to interface the LCR meter to high voltage bias sources. The effects of the added circuitry are studied theoretically, and the CV measurement accuracy is verified with experimentation. High voltage capacitance voltage measurements are presented for both silicon and SiC power MOSFETs.

High-megawatt Power Conditioning Systems (PCSs) are required to convert the low-voltage produced by fuel cell modules in central station scale plants to the very much higher voltage levels required for delivery to the grid. As part of a NIST/DOE Interagency Agreement, advanced PCS architectures, circuit topologies, and component technologies are being evaluated to identify technologies requiring development to meet the fuel cell power plant PCS cost goals of $40-$100/kW. In addition, several industry, government, and university programs are being initiated to in part support these fuel cell power plant PCS goats.

This paper presents the results from a parametric simulation study that was conducted to optimize the performance of 100 A, 10 kV, 20 kHz half-bridge SiC MOSFET/JBS power modules. The power modules are being developed by the DARPA WBGS-HPE Phase II program and will be used in the 13.8 kV, 2.75 MVA SSPS developed in the HPE Phase III program. The simulations are performed using recently developed and validated physics-based electrical and thermal models. The total device active areas and the various gate resistances and inductances are optimized in order to minimize overall power dissipation. A detailed description of the loss mechanisms and the simulation results for a representative SSPS topology is also presented.

This paper presents a test system developed for long-term stability characterization of 10 kV Silicon Carbide (SiC) power MOSFETs and SiC diodes under 20 kHz hard switching conditions. The system is designed to test a single power switch and a single power diode for continuous or burst switching conditions up to 5 kV and 5 A. The test system includes a 4.5 kV to 5 kV boost converter to emulate a 22.5 kW hard switching power converter. An additional DC-DC converter is used to recover the power processed by the boost converter. The design criteria, simulation, and construction of the test system are discussed in this paper and the system operation is demonstrated using various high voltage devices including 4.5 kV Silicon IGBTs, 10-kV SiC MOSFETs and 15 kV stacked silicon diodes.

Circuit simulator model validation procedures and results are presented for SiC power MOSFETs. The characteristics discussed include on-state conduction, resistive load switching, inductive load switching, and high voltage depletion capacitance. The validation procedures are performed using a script written in the AIM language that is incorporated in the Saber(R)(lozenge) circuit simulator. The script uses the model parameter sets from the IGBT Model Parameter ExtrACTion (IMPACT) tools to perform simulations and then compares the simulated results with measured characteristics. Example validation results are presented for recently developed 5 A, 10 kV SiC power MOSFETs demonstrating for the first time the model performance at the full application switching voltage (5 kV for the 10 kV devices).

A software-based high-voltage curve tracer application for SiC device characterization is presented. This flexible application interface is developed to define testing parameters needed to control the hardware of a custom-made 25 kV-capable SiC characterization test bed. Data acquisition is controlled for optimum resolution, and I-V characterization is computed by means of a user-defined time interval based on the shape of the applied power pulses. Both voltage and current waveforms are displayed for each data point captured to allow the user to observe transient effects. Additionally, the software allows achieving some or all of these transient waveforms. Acquired results are shown to demonstrate functionality and flexibility of the new system

Introduction Advances in MicroElectroMechanical Systems (MEMS) technology over more than a decade have made it possible to create microstructures that can be used as microsensors and microactuators for a wide range of applications. The microhotplate, [1], is one such microstructure that can be used as a basic building block for a variety of microsensors. In this paper, a technologyindependent microhotplate fabrication and characterization method is described, primarily aimed at submicron low-voltage embedded gas sensor System-on-a-Chip (SoC) design applications.

A new on-chip electrostatic discharge (ESD) protection scheme is demonstrated for microelectromechanical systems (MEMS)-based embedded sensor (ES) system-on-a-chip (SoC). The ESD protection scheme includes ground-referenced protection cells implemented with novel multifinger thyristor-type devices for (1) input/output (I/O) protection; (2) power supply clamp; (3) protection at the internal sensor electrodes. The I-V characteristics of the thyristor-type protection cells are adjusted to provide an optimum ESD protection per unit area. Transmission line pulsing (TLP) measurements and ESD testing show superb high conductance on-state I-V characteristics with no latch-up problem when thyristor-type devices are subjected to an ESD event, while very low leakage current is obtained at the SoC operating voltage.

A full electro-thermal simulation of a three-phase space-vector-modulated (SVM) inverter is performed and validated with measurements. Electrical parameters are extracted over temperature for the insulated gate bipolar transistor (IGBT) and diode electro-thermal models. A thermal network methodology that includes thermal coupling between devices is applied to a six-pack module package containing multiple IGBT and diode chips. The electro-thermal device models and six-pack module thermal model are used to simulate SVM inverter operation at several power levels. Good agreement between model and measurement is obtained for steady state operation of the three-phase inverter. In addition, transient heating of a single IGBT in the six-pack module is modeled and validated, yielding good agreement

A latest developed normally-off SiC JFETs has been characterized under static and dynamic operating conditions. Two application oriented inverter circuits were constructed for additional tests under and soft- and hard-switching conditions. The single-phase soft-switching inverter was running at 100 kHz, and the three-phase hard-switching inverter was running at 15 kHz. The unique feature of the inverter operating in synchronous rectification mode has been observed. Without synchronous rectification, the freewheeling diode voltage drop is a fixed voltage plus a resistive voltage. The fixed voltage at zero current is about 1 V for the tested SiC Schottky diodes, and the resistive voltage drop portion is highly dependent on the temperature. With synchronous rectification, the voltage drop is the product of the on-drop resistance and the drain current of the JFET, which can be controlled with the chip area. In the experimental case, the measured voltage drop was 1 V with JFET conducting in reverse direction and 2 V with diode forward conducting. Thus the new generation SiC VJFET device allows high-efficiency inverter operation with reduction of the conduction loss by synchronous rectification and the reduction of switching loss with soft switching.

10 kV, 123 mOmega(.)cm(2) Power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R-on,R-sp, compared to a previously reported value, was achieved by using an 8 x 10(14) cm(-3) doped, 85-mum-thick drift epilayer. An effective channel mobility of 22 cm(2)/Vs was measured from a test MOSFET. A specific on-resistance of 123 mOmega(.)cm(2) were measured with a gate bias of 18 V, which corresponds to an E-ox of 3 MV/cm. A leakage current of 197 muA was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 x 10(-3) cm(2). A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications.