Dynamic logic is a high-speed technology that was previously used in mature technologies, but lost popularity due to the increased leakage and process variations in advanced technologies. However, the recent popularity of circuits running in the cryogenic region provides a new opportunity for dynamic operation, thanks to the reduced leakages at such low temperatures. This paper revisits dynamic logic as a true candidate for high-performance and energy-efficient circuits for cryogenic operation in nanoscaled technologies. The paper first overviews and analyzes transistor operation at cryogenic temperatures and how it influences digital circuit design targeted to this regime. With these effects in mind, the use of dynamic logic families, including the classical dynamic (NORA) logic and the recently introduced and families, are examined under cryogenic operation, showcasing improved performance and power efficiency. Measurements conducted on a 16FinFET test chip validate their operation at low temperatures down to 4, with supply voltages ranging 0.4–0.8-V. Furthermore, the considered dual mode logic families exhibit performance enhancements of up to 26% in dynamic mode and power efficiency increases up to 53% in static mode, compared to CMOS.

IoT devices often face conflicting power and performance requirements. They might be required to dynamically switch between (1) power-saving battery-powered mode, (2) ultra-low harvested power mode, and (3) high-performance real-time operation. In this work, we present a novel Triple Mode Logic (TML) that addresses the aforementioned requirements and enables ultra-low power mode for purely harvested operation, energy-saving mode for battery-powered operation, and accelerated mode for high-performance operation. Simulation results of several TML benchmarks indicate that in ultra-low power mode, TML reduces the power consumption by approximately five orders of magnitude compared to CMOS. In normal static (energy-saving) mode, TML consumes up to 35% less energy than Dual Mode Standard Cell (DMSC) state-of-the-art solution. In normal dynamic (high-performance) mode, TML is faster than the DMSC solution by up to 43%.

Cryogenic operation of cutting-edge applications creates opportunities for conducting further optimization beyond conventional technology scaling. Optimal design in cryogenic environments requires extensive characterization efforts, made possible by implementing various characterization methodologies tailored for different devices and aspects of VLSI design. This paper explores cryogenic characterization methodologies and the impact of robust measurement infrastructure. Transistor and standard cell characterization methodologies are discussed thoroughly with great emphasis on the unique properties of each method. Since reliable cryogenic measurement environments are crucial for achieving high quality results, two types of measurement infrastructures are shown: dipstick and cryogenic chamber. Although both implementations allow for cryogenic measurements across wide temperature range, choosing the right configuration relies on a trade-off between system complexity and result quality.

Cryogenic operation is the backbone of many cutting edge applications. Significant work has been done to characterize and model all cryogenic effects for creating a reliable, robust and efficient cryogenic design across a wide range of technologies and process nodes. This paper presents the main phenomena that alter device behaviour, their implications on cryogenic-specific integrated circuit design, and the variations between each technology node.

Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elements in static or dynamic mode, it is possible to significantly improve performance at the cost of a limited increase in energy consumption, and vice versa. In this letter, for the first time, we design, fabricate in a commercial 16-nm FinFET process, and evaluate in silicon FlexDML, an adaptively configurable arithmetic unit. FlexDML comprises several DMLBricks, $2\times 2$ and $4\times 4$ DML-based multiplier units, as well as DML-based shifters and adders. FlexDML is capable of performing several arithmetic operations with flexible wordlength, such as $N\times N$ -bit, two $(N/2)\times N$ -bit or $N\times (N/2)$ -bit, four $(N/2)\times (N/2)$ -bit, and so on multiplications, as well as shifts and inner product calculations. All DMLBricks can be operational at the same time, increasing the hardware utilization to the level unattainable in typical designs that support variable wordlength. FlexDML is the first to support a pipeline multimode, where the DML mode is set separately for each pipeline stage, thus enabling more flexible ED optimization. FlexDML achieves up to 41% performance improvement in dynamic mode, and power savings of about 23% in static mode, compared to CMOS implementation.

In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting single-instruction-multiple-data (SIMD)-like systems is proposed. The design introduces improvements at both the architecture and logic gate levels, by capitalizing on their synergistic combination. At the architecture level, the multiplier design is adapted to accommodate diverse computations based on the level of the input data parallelism. The main novelty is the incorporation of three different acceleration or bypass mechanisms jointly. The configurable multiplier has three variable precision configuration options: a $32\times 32$ -bit, two $16\times 16$ -bit, and four $8\times 8$ -bit multipliers. This bypassing architecture seamlessly integrates DML logic, which supports two modes of operation: a high-performance dynamic mode and a low-energy consumption static mode, with smooth mode switching capabilities. By optimizing the DML mode based on the multiplier’s bit-width, the design enhances active computational block utilization, overall performance, and energy efficiency. In the dynamic mode, the DML implementation achieves an average performance improvement of 15% for the 32-bit, 8% for the 16-bit, and 7% for the 8-bit multipliers compared to the CMOS implementation. In the static mode, the DML implementation demonstrates an average energy reduction of 28%. When running in combined mode, where the 32-bit multiplier operates in dynamic mode for acceleration and the 8-bit multiplier operates in static mode for energy savings, the DML implementation exhibits an average overall performance gain of 15% and up to 18% lower energy consumption. The non-trivial semi-automation flow utilized for the complex implementation of the proposed architecture is also presented.

Dual Mode Logic (DML) enables the dynamical operation of digital circuits optimized for energy-delay efficiency. Here, for the first time, DML is examined under cryogenic conditions, and its characteristics are evaluated for future applications. As a proof-of-concept, a DML testchip designed in 65nm technology was measured under cryogenic temperatures down to 4K. Measurements at supply voltages from 0.8V to 1.2V and temperatures ranging from 300K (room temperature) to 4K, confirm the effectiveness of DML under extreme temperatures.

A technique to mitigate timing errors induced by power supply droops is featured. We propose an inverter-based droop detector as well as dual mode logic (DML) to achieve a droop-resistant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to process/voltage/temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved. A prototype instantiating a demo of the scheme was fabricated in a TSMC 65 nm process, incorporating a simultaneous three-level detector and a DML-based ripple carry adder (RCA). The droop detector consumes 62 $\mu \text{W}$ , has a response time of 2 ns, and an accuracy of 0.9% of Vdd, making it one of the fastest, most accurate, and lowest power droop detectors in its class. The RCA can maintain timing for voltage droops up to 400 mV. A potential supply level reduction of up to 12% was demonstrated for the RCA, and a similar reduction could be achieved with larger-scale DML digital circuits as well.

Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from - 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.

In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique characteristics of the FD-SOI technology has enormous potential to design energy-efficient adaptive digital circuits operating on an ultra-wide voltage range. As a main result, we demonstrate that single well option offered by the FD-SOI greatly extends the low-granularity energy-delay (E-D) optimization capability of DML-based designs. By exploiting the above implementation strategy, a 16-bit DML carry skip adder reduces its energy consumption by 41% and increases its speed of about 26% when changing its operation mode (from static to dynamic) at 0.4V as compared to its equivalent standard CMOS design.

In the past, Pass Transistor Logic (PTL) was widely used due to benefits in terms of speed and power consumption coming from the reduced number of transistors. However, issues such as threshold drop across the single-channel pass transistors and high sensitivity to process variations have prevented the use of PTL in advanced nanometer technologies. In this paper, we propose a novel logic family named Dual Mode Pass Logic (DMPL), which allows for high speed and low power consumption while maintaining robustness down to the sub-threshold voltage region. The DMPL effectively combines PTL to reduce energy and power consumption along with the flexibility of Dual Mode Logic (DML) to switch to a speed improved operating mode according to the system requirement. Simulation analysis performed on basic NOR/NAND gates implemented in 16 nm Finfet technology demonstrates that DMPL can reduce energy and power by 33% and 42% as compared to logically equivalent static CMOS design. Moreover, running frequency of a DMPL circuit can exceed that of its static CMOS counterpart by 84% when speed is mandatory. Additionally, DMPL gates demonstrate similar robustness as static CMOS implementations under process and temperature variations at lower supply voltages.

The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16×16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operate digital gates either in the static mode to save energy, or in the dynamic mode to increase speed albeit with a higher delay or energy consumption, respectively. We showed that on-the-fly switching of critical paths between the static and dynamic modes enabled system self-adaptation to computational needs achieving both high speed and low energy consumption. In this paper, for the first time we show that the mixed mode operation of a DML based datapath can efficiently reduce design sensitivity to process variations at near threshold voltages. Specifically, the number of gates operating in the dynamic mode (when the datapath is switched to the high-performance mode) is selected as a function of the process corner. The number of dynamically operated gates can be adjusted during the post-silicon phase or at run-time with an architectural level solution. In a basic proof of concept, simulations of a chain of 20 NAND/NOR gates demonstrated that process variations were successfully alleviated by utilizing an optimal configuration of the chain. The DML design can meet CMOS TT performance requirements in the SS corner and save energy by 18% in the FF corner. A 64-bit ripple carry adder (RCA) confirmed the advantages of DML over CMOS for different optimization points.