Sparse General matrix multiplication (SpGEMM) is a fundamental kernel in many scientific and engineering fields, including Artificial Intelligence (AI). However, its intrinsic computation complexity presents substantial challenges, making efficient hardware implementation particularly difficult. This paper proposes SPARCAM, a novel SpGEMM accelerator, developed and optimized for very energy-efficient AI edge applications. SPARCAM is designed using low-power dense Gain Cell embedded DRAM (GC-eDRAM) technology, a processing near memory paradigm, and a modified outer product matrix multiplication algorithm. Despite its quite limited peak theoretical performance, SPARCAM achieves very high energy efficiency due to its low-power architecture and almost 100% utilization of its computing resources. Designed in a commercial 28 nm FDSOI technology, SPARCAM achieves 13.9x speedup over a high-performance embedded CPU when processing large-scale sparse matrices. When multiplying limited-size sparse matrices, SPARCAM obtains 193x speedup over highperformance GPU. SPARCAM reaches about 4.3 orders-of-magnitude, on average, higher energy benefits, and 1892x, 181x, 2x, and 3471x, higher energy efficiency (over CPU) compared with state-of-the-art SpGEMM accelerators SpArch, OuterSPACE, MatRaptor, and high-performance GPU, respectively.

Silicon-based analog neural networks physically embody the ideal neural network model in an approximate way. We show that by retraining the neural network using a physics-informed hardware-aware model one can fully recover the inference accuracy of the ideal network model even in the presence of significant non-idealities. This is way more promising for scalability and integration density than the default option of improving the fidelity of the analog neural network at the cost of significant energy, area, and design overhead, through extensive calibration and conservative analog design. We first present a physics-informed hardware-aware model for a time-domain vector-matrix multiplier implemented with single-transistor floating-gate memory cells that explicitly accounts for two dominant non-idealities of the physical implementation - capacitive crosstalk and bit-line voltage drop - and integrates seamlessly with modern deep-learning workflows. The model discretizes each operation into adaptive time slots, processes activation patterns in parallel, and accumulates their contributions to predict effective multiplier outputs. Using measurements from a 16x16 silicon array, we calibrate the model, show that crosstalk is layout-dependent and often dominant, and introduce an improved weight-extraction procedure that doubles signal-to-error ratio versus an ideal vector-matrix multiplier model. Finally, we show that by training silicon-based analog neural networks using an hardware-aware model in the forward pass we can recover the accuracy of the ideal software networks across three architectures – custom MLP on low-resolution MNIST, LeNet-5 on MNIST, and a VGG-style CNN on CIFAR-10 - establishing a complete design-to-deployment workflow for time-domain analog neuromorphic chips.

Content-addressable memories (CAMs) are a class of associative memories known for their capability to perform massively parallel comparisons between an input query pattern and the entire memory content. In the past decade, the increasing demand for high-performance and energy-efficient computing systems has generated significant interest in non-volatile CAMs (NV-CAMs) based on emerging non-volatile memory devices. In this work, we propose a novel non-volatile, precharge-free CAM (NV-PCAM) scheme based on double-barrier magnetic tunnel junctions (DMTJs). When compared to its counterparts, NV-PCAM presents competitive figures of merit in terms of area, speed, and energy efficiency, while also ensuring low search error rates. We also provide a complete class of voltage-divider-based NV-CAM cells for benchmark comparison. All schemes are designed and laid out using a 65 nm process and evaluated under Monte Carlo and process-voltage-temperature (PVT) simulations. Through Monte Carlo simulations, the proposed NV-PCAM demonstrates up to 81% and 85% lower search energy than NV-NOR and NV-NAND, respectively, as well as a 61% and 16% improvement in terms of search delay with a compact cell area footprint.

Application domains, such as machine learning and big data analytics, impose significant computational challenges to contemporary Von Neumann architectures. To address this issue, logic-in-memory (LiM) has been raised as a promising alternative that targets computing within memory arrays, aimed at alleviating the memory wall, optimizing data transfer, and enabling massive parallelism. Spin-transfer torque magnetic tunnel junction (STT-MTJ) based memory is an emerging memory technology that enables efficient processing using memory. This paper proposes AM5, a novel LiM architecture leveraging MRAM NAND crossbar technology to support in-memory arithmetic operations efficiently. The proposed LiM scheme is designed using a commercial 28 nm process node and a Verilog-A-based double-barrier MTJ compact model. Evaluation results show that AM5 consumes about 98 fJ/40.7 fJ/DMTJ per evaluation/write cycle (4.2-4.4 ns/1.9 ns). Additionally, the proposed architecture proposes an in-situ error correction mechanism to mitigate variability, yielding reliable arithmetic operations. These findings show better energy (similar to 6 x lower, on average) and competitive latency (similar to 1.3 x faster, on average) figures of AM5 compared to other LiM designs based on MTJ-based technology. When used as a LiM unit to perform inference in adder attention Vision Transformer networks, AM5 consumes about one-tenth of the energy required by a processor-centric unit.

Probabilistic computing with p-bits is emerging as a computational paradigm for machine learning and for facing combinatorial optimization problems (COPs) with the so-called probabilistic Ising machines (PIMs). From a hardware point of view, the key elements that characterize a PIM are the random number generation, the nonlinearity, the network of coupled probabilistic bits, and the energy-minimization algorithm. Regarding the energy-minimization algorithm in this work we show that PIMs using the simulated quantum annealing (SQA) schedule exhibit better performance as compared to simulated annealing and parallel tempering in solving a number of COPs, such as maximum satisfiability problems, the planted Ising problem, and the traveling salesman problem. Additionally, we design and simulate the architecture of a fully connected CMOS-based PIM that is able to run the SQA algorithm having a spin-update time of 8 ns with a power consumption of 0.22 mW. Our results also show that SQA increases the reliability and the scalability of PIMs by compensating for device variability at an algorithmic level enabling the development of their implementation combining CMOS with different technologies such as spintronics. This work shows that the characteristics of the SQA are hardware agnostic and can be applied in the codesign of any hybrid analog-digital Ising machine implementation. Our results open a promising direction for the implementation of a new generation of reliable and scalable PIMs.

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures.

Content-addressable memory (CAM) is a specialized memory architecture designed for fast data searches, allowing a one-clock-cycle comparison between the search input and the entire memory content. In this work, a low matchline voltage swing CAM is proposed to reduce the search power consumption while maintaining high-speed search operations. Low voltage swing in the matchline is enabled by introducing extra circuitry in the conventional CAM cell. By means of comprehensive Monte Carlo and post-layout simulations using a commercial 65nm node, we show that the proposed CAM cell design allows for robustness against process, voltage, and temperature variations without the need for dedicated matchline sense schemes. Compared to conventional precharge high NOR-type CAM, the proposed design achieves 42% higher speed and 29.1% less energy consumption. Post-layout results demonstrate that the proposed CAM operates reliably at 0.6V, maintaining performant and reliable search operations across a wide temperature range.

Binary Neural Networks (BNNs), where weights and activations are constrained to binary values (+1, -1), are a highly efficient alternative to traditional neural networks. Unfortunately, typical BNNs, while binarizing linear layers (matrix-vector multiplication), still implement other network layers (batch normalization, softmax, output layer, and sometimes the input layer of a convolutional neural network) in full precision. This limits the area and energy benefits and requires architectural support for full precision operations. We propose PiC-BNN, a true end-to-end binary in-approximate search (Hamming distance tolerant) Content Addressable Memory based BNN accelerator. PiC-BNN is designed and manufactured in a commercial 65nm process. PiC-BNN uses Hamming distance tolerance to apply the law of large numbers to enable accurate classification without implementing full precision operations. PiC-BNN achieves baseline software accuracy (95.2%) on the MNIST dataset and 93.5% on the Hand Gesture (HG) dataset, a throughput of 560K inferences/s, and presents a power efficiency of 703M inferences/s/W when implementing a binary MLP model for MNIST/HG dataset classification.

A design for a cost-effective one-port patch antenna for high-frequency (20GHz) dielectric spectroscopy is presented. The sensor comprises a microstrip input line, a quarter-wavelength transformer for impedance matching, and a patch antenna with a milled channel adjacent to its radiating element, allowing fluids to influence its resonant frequency. A circuit model explains the operating principle, showing that shifts in resonant frequency correspond to variations in the real part of the fluid's permittivity. The sensor's performance is assessed through finite element method (FEM) simulations under various material conditions. Results indicate that the sensor's response is predominantly governed by the real part of permittivity, with minimal impact from dielectric losses. Calibration using reference fluids in simulations yields a predictive model with high accuracy (R2> 0.99). Experimental validation and prototyping are planned for future work.

The Ternary Content Addressable Memory (TCAM) is a crucial component of satellite communication systems. Space-oriented TCAMs face unique challenges, as they must operate within a very limited energy budget and are susceptible to high Soft Error Rates (SER) due to ionizing particle radiation. The Dual Interlocked Storage Cell (DICE) based memory is capable of withstanding soft errors. However, its reliability diminishes in presence of multiple node upsets. Moreover, recent studies indicate that DICE resilience to even single-node upsets degrades in advanced technology nodes. This issue is further exacerbated by the scaling of the supply voltage to reduce power consumption. In this paper, we propose SpaceCAM, a DICE-based TCAM that overcomes the above limitations and enables aggressive voltage scaling while withstanding multiple node upsets in each memory row. SpaceCAM enables soft error tolerance by applying an approximate rather than an exact search. It tolerates up to 5 soft errors per 144-bit row, provided the minimum Hamming distance between stored data patterns (such as the Active Control List (ACL) rules) is 26. When designed using a 16nm FinFET commercial process, SpaceCAM $144\times 512$ -bit memory core operates at a supply voltage of as low as 350mV, consuming 2mW while running at 500MHz.

Smart tags are compact electronic devices affixed to or embedded into objects to facilitate identification, monitoring, and data exchange. Consequently, secure authentication of these tags is a crucial issue, as objects must reliably verify their identity before sharing sensitive information with other entities. The application of Physical Unclonable Functions (PUF) as a device's “digital fingerprint” has attracted significant attention, yet existing PUF-based authentication methods exhibit security vulnerabilities, either due to the authentication protocol itself or the limited reliability of the PUF technology used. Moreover, there has been a considerable focus on the software aspect, often overlooking the critical role of hardware design, which can become a target for attacks aimed at compromising the device's identity or act as a hindrance in the manufacturing process. In light of these points, this paper introduces an identification tag architecture that leverages PUF technology, focusing on authentication. This architecture features a straightforward but efficient authentication protocol, underpinned by a new and highly stable PUF model. The overall architecture encompasses particular hardware implementation aspects that significantly simplify the tag's enrollment phase and minimize vulnerabilities to attacks. The paper also describes a prototype of this identification tag and provide detailed insights into its application.

Air pollution is a global problem and it affects the health of millions of people every day, not to mention the damage it also causes to the environment. It is still an issue that does not reach all world territories. In many countries, monitoring air quality is regulated, standardized, and mandatory. However, it remains underdeveloped, leaving countries with insufficient monitoring of pollution levels. Our work aims to develop a low-cost mobile air pollution monitoring system. The system was designed to monitor environmental factors such as: temperature and relative humidity; as well as common pollutants CO, NO2, SO2 and O-3. The first phase of our project led to the development of a prototype deployed at a fixed site to collect air pollutant data, store, and analyze it. The results qualitatively demonstrated the good performance of the sensors and of the overall system, guiding us in identifying additional features and improvements needed to enhance its functionality. These results contributed to a modular, compact, and geo-referenced monitoring system.

This paper introduces a physical unclonable function (PUF) based on a differential array of minimum-sized PMOS devices. Each response bit is obtained by comparing the two analog outputs of the differential array through a dynamic comparator with a trimmable offset. This offset is effectively used to mask potentially unstable response bits. To further improve PUF reliability, spatial majority voting is also implemented, resulting in a near-zero (<3.12×10−9) bit error rate (BER) at 1.2 V and 25 °C. Under variations in supply voltage (0.8–1.3 V) and temperature (0–75 °C), the native bit error rate of 3.5% is reduced to 9.73×10−4 after stabilization, consuming only 1.37 pJ per output bit.

Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS technology and comprehensively evaluated under Monte Carlo simulations and PVT variations. The proposed scheme was built using MIM capacitors and transistor-based capacitors, and it includes Verilog-based calibration algorithms. The proposed offset calibration is benchmarked, in terms of precision, calibration time, energy consumption, delay, and area, against prior calibration techniques: current injection via gate biasing by a charge pump circuit and current injection via parallel transistors. The evaluation of the offset calibration schemes relies on Analog/Mixed-Signal (AMS) simulations, ensuring accurate evaluation of digital and analog domains. The charge pump method achieved the best Energy-Delay Product (EDP) at the cost of lower long-term accuracy, mainly because of its capacitor leakage. The proposed scheme demonstrated superior performance in offset reduction, achieving a one-sigma offset of 0.223 mV while maintaining precise calibration. Among the calibration algorithms, the window algorithm performs better than the accelerated calibration. This is mainly because the window algorithm considers noise-induced output oscillations, ensuring consistent calibration across all designs. This work provides insights into the trade-offs between energy, precision, and area in dynamic comparator designs, offering strategies to enhance offset calibration.

In this paper, a highly reliable multi-bit physically unclonable function (PUF) is proposed. The solution relies on an already tested two-transistor (2T) sub-threshold voltage divider as core circuit along with a multi-bit architecture able to carry out two highly stable bits from three bits generated by a proper entropy quantization. Twenty measured samples of the bitcell core were used to fit a customized Verilog-A model, which was then imported into Cadence Virtuoso environment for the architecture-level analysis. The proposed solution was tested across Monte Carlo simulations at both golden key (GK) and different environmental conditions, while also including the effect of noise. Simulation results prove the effectiveness in generating two highly stable bits for each cell after spatial majority voting and best stability selection. Indeed, no instability was observed in the 0-50 degrees C temperature range for the two output bits.

The growing need for approximate matching in data-intensive applications, such as data analytics, machine learning, deep learning, and computational genomics has driven the proposal of our Hamming distance (HD) tolerant content-addressable memory (HD-CAM). HD-CAM features a modified nor-type associative memory cell that leverages the discharge speed of the matchline (ML) to directly measure the HD between the stored and the query patterns. This novel approach enables efficient in-memory approximate matching. The proposed design was fabricated in a 65-nm technology, running at 125 MHz with an operating voltage of 1.2 V and consuming approximately 0.2 fJ/bit/search at room temperature. HD-CAM features a user-programmable HD tolerance threshold, making it particularly efficient for compare-intensive applications, such as genome analysis, text processing, and database processing. Silicon measurements demonstrate that HD-CAM maintains F1 score above 90% under process, voltage, and temperature (PVT) variations across a range of HDs.

This work presents a non-volatile content-addressable memory (NV-CAM) based on double-barrier magnetic tunnel junction technology (DMTJ). Unlike state-of-the-art NV-CAM designs that present low-performance updates, our NV-CAM allows energy-efficient, high-performance search and update operations. This makes it well-suited for applications requiring a high frequency of searches/updates, such as associative processors. The NV-CAM hybrid CMOS/DMTJ was designed using a commercial 65nm CMOS technology and a Verilog-A-based DMTJ compact model. The NV-CAM evaluation was carried out by employing Monte Carlo simulations while accounting for process variations. Simulation results show that our NV-CAM presents competitive figures of merit compared to state-of-the-art design. Our NV-CAM presents energy-efficient operations and reduces the update and search delay by about 71% and 75%, respectively, compared to other NV-CAMs.

Low-Power high-performance content-addressable memories (CAMs) are important components in modern computing systems. In this work, we present a robust CAM that overcomes the power and performance limitations of conventional precharge-based CAMs. The proposed static transmission gate-based (STAT-TG) CAM design achieves low-power operation comparable to NAND CAMs while maintaining search speeds rivaling those of NOR CAMs. The STAT-TG CAM was designed using a 65nm CMOS technology and comprehensively evaluated under extensive Monte Carlo simulations. Compared to conventional CAMs, the STAT-TG CAM is 14% faster than NAND CAM, while consuming only 25% of the energy per operation relative to NOR CAM. This makes STAT-TG CAM a promising solution for high-performance yet energy-efficient applications.

This paper explores a class of highly stable staticmonostable physically unclonable functions (PUFs) based onstacked sub-threshold voltage dividers between two nominallyidentical sub-circuits as bitcell core block. More specifically,compared to our previous works where two-transistor (2T) andfour-transistor (4T) voltage divider based PUFs were presentedand analyzed, here we propose two novel topological variantsbased on six-transistor (6T) and eight-transistor (8T) solutionswhich arise from adopting a proper reverse gate-biasing strategywithin the stack with the aim of improving the resilience to on-chip noise and voltage variations, while keeping the area overheadlow. These novel solutions, along with those already proposed,were tested in 180-nm CMOS technology. Raw measurementsshow a nominal (at 1.8 V and 25degree celsius) bit error rate (BER) of0.15% and 0.08% for the 6T- and 8T-based solutions, respectively,along with a BER variation of 0.016% and 0.002% per 0.1 V.With the implementation of a simple masking technique basedon measurements at low supply voltage (VD D=0.3 V at 25degree celsius)along with a temporal majority voting (TMV) scheme, a BER of0.006% and lower than 9.77x10(-5)%, which is the minimumobservable BER for the adopted statistical set, was observed forthe 6T-, and 8T-core based implementations, respectively, witha corresponding masking ratio of 8.71% and 7.59%. This isachieved with an area per bit of 5,174F(2)(6T solution) and6,994F(2)(8T solution)