A method for reducing circuit Sensitivity to Single event upsets in programmable logic devices, involves identifying Single event upset Sensitive gates within a single event upset Sensitive Sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each Single event upset Sensitive Sub-circuit So identified.

The integration of fully silicided gates on a high-k dielectric in a standard process flow offers a solid alternative to the conventional Poly/SiON devices. In this work, we provide an extensive analysis of the module yield extracted for such devices highlighting the need for specific additional alarm flags without which some integration problems might be overlooked. The impact at the circuit level is studied and supported by modeling work on simple ring-oscillators.

We report the simultaneous improvement of both on- and off-properties for n- and p-channel MOSFETs by means of carbon co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with phosphorus-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (REXT) vs. effective channel length (Leff) trade-off are examined. To obtain the full benefit of carbon co-implantation, we recommend adjusting pocket, highly doped drain (HDD) and spacer parameters

We demonstrate for the first time the integration of metal gate electrode and non-melt laser annealed junctions in both NMOS and PMOS transistors. We report the highest drive current so far in laser annealed devices with good Short Channel Effects (SCE) control down to 40nm gate length. Overlap length is quantified by CV and SSRM, values of 2 nm for both NMOS and PMOS laser-annealed transistors are reported for the first time.

A thermo-mechanical stress model (TMS) is presented to explain the impact of sub-melt laser anneal (LA) on SiON dielectric and on the overall transistor performance. An Lgmin reduction of 15nm/5nm for nMOS/pMOS over our poly-Si/SiON reference, with 8% capacitance and 10% source and drain resistance (RSD) improvement, is demonstrated. Best device performance and NBTI immunity are reached by lowering the laser power and optimizing the nitrogen and fluorine profile. This minimizes the increase of Si dangling bonds at the SiON/Si interface and the oxide fixed charges, generated by the thermo-mechanical stress (TMS) during the LA fast thermal gradient. The full potential of LA is demonstrated by skipping the RTA. An Lgmin gain of 25nm/20nm is achieved for metal gate nMOS/FUSI gate pMOS devices over the junction RTA reference. Optimal 0.26 fF/mum overlap capacitance values (at Vdd= | 1 | V), 18%/ 23% for nMOS/pMOS lower CV/I product and pMOS improved RSD are demonstrated

In this letter, the feasibility of split-capacitance-voltage (C-V) measurements in the RF range is demonstrated. These RF/split-C-V measurements show excellent agreement with the values obtained by the low-frequency conventional technique but without presenting any noticeable degradation due to gate leakage

In this paper, we investigate the impact of replacing tungsten (W) by a Cu-based contact module. Our experiments show that a 50% reduction in contact resistance can be obtained. This is attributed to both the choice of barrier as well as filling material. An increased drive current is measured on narrow transistors with single contacts. The intrinsic gate oxide reliability is not compromised. Results on demonstrator ring oscillator structures show how the parasitic contribution to the transistor series resistance will increasingly impact circuit delay and power dissipation upon scaling. Cu is presented as a viable solution to postpone these effects by at least one node

A comprehensive analysis of operational tall triple-gate MuGFET ring oscillators (ROs) is presented for the first time. Device geometries, process options and best inverter layout are discussed based on measured power and delay. A MOS model 11 based macro-model has been calibrated and correlated to hardware to enable a study on work-function tuning, conformal S/D extensions, strain engineering, raised S/D extensions and their impact at circuit level. Performance is benchmarked against reference bulk-planar LSTP and HP CMOS processes options to determine MuGFETs applicability opportunities. Finally, a new metric is used to assess CMOS technologies circuit potential, demonstrating the superior characteristics of MuGFET devices for low-power (LP) and for low-operational power (LOP) applications

In this work, we present a methodology for characterizing the impact of circuit layout style, technology elements (low-k material, resist choice), device engineering and temperature on the circuit power-delay trade-off. We provide experimental results supported by modeling work, showing significant improvements in circuit speed at fixed power levels resulting from improvements in layout style and technology. For instance, the use of a more advanced resist at gate level leads to a 3x reduction in static power dissipation at a given ring-oscillator (RO) delay or in other words close to a 10% improvement in the inverter delay for a similar static power dissipation.

In this paper, authors investigated for the first time the effective mobility (mueff) in short-channel FinFET transistors. Dedicated test structures for radio-frequency (RF) split C-V measurements enabled short-channel FinFET C-V measurements, and consequently, accurate effective channel length (Leff) calculation for reliable muff extraction. muff is extracted for FinFETs down to dimensions of 60nm fin height, 25nm fin width and 70nm Lff, with poly-Si/MOCVD-TiN gate stacks on SiON dielectrics. Promising non-degraded long/short channel hole mobility behavior is reported, whereas electron mobility decreases with Lff

This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-V T applications) have been achieved (17ps at V DD =1.1V and 20pA/mum I off ), meeting the ITRS 45nm node requirement for low power CMOS

This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of - 14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

A 90nm CMOS technology has been used as the baseline for a low-cost RF-CMOS platform, with improved analog/RF performances of the active and passive devices. The 65 nm gate length NMOS exhibits 240GHz peak f/sub max/ and 170GHz peak f /sub T/. A peak Q of 40@5GHz is measured for a symmetrical 2.7 nH above-IC inductor. This combination leads to a world record performance of a monolithic 5 GHz RF CMOS low noise amplifier presenting a very high gain of 18dB and very low noise figure of 1.5dB, for only 4.8mW power consumption.

A methodology for the optimal parasitic-aware design of RF power amplifiers toward maximum power efficiency is presented. It is based on a template-driven simulation-based optimization approach, including the effect of all device parasitics (transistors, passives) during the sizing. The combination of expert knowledge (in the template) with a state-of-the-art evolutionary algorithm results in a highly flexible and optimal sizing methodology tailored to RF circuits. Parasitic information is obtained through interaction with device profilers. The methodology is implemented in a fully featured software tool called M-DESIGN and is applied to the optimal sizing of a two-stage Class E power amplifier for maximum efficiency. The complete sizing was obtained in less than one hour of CPU time. Moreover, the constraint templates that were used are presented and discussed. An amplifier manufactured in a commercial 0.35-/spl mu/m 5M2P CMOS process and sized using the proposed methodology shows a maximum value of 67% for the drain efficiency (DE) versus 66% simulated. Measurement results show that it works at 850 MHz and has a maximum output power of 30 dBm at 2.3 V. The power-added efficiency (PAE) is always greater than 60% for an output power above 160 mW and a maximum PAE of 66% is achieved.

Hot-carrier stress impact on the analogue/RF performances of a state-of-the-art 90nm RF-CMOS technology, demonstrated on RF-circuits operating up to 5Ghz, is shown for the first time in a 900MHz LNA biased in moderate inversion. The Trade-off between low-power consumption and lifetime is discussed, addressing limitations and pointing to possible solutions.

The problems with the CV characterization on very leaky (thin) nitrided oxide are mainly due to the measurement precision and MOS gate dielectric model accuracy. By doing S-parameter measurement at RF frequency and using simple but reasonably accurate model. we can obtain proper CV curves for very thin nitrided gate dielectrics. Regarding the measurement frequency we propose a systematic method to find a frequency range in which we can select measurement frequencies for all biases to obtain a full CV curve. Moreover, we formulated the first order relationship between the measurement frequency range and the test structure design for CV characterization. With the established formulae, we redesigned the test structures and verified that the formulae can be used as a guideline for the test structure design for RFCV measurements.

A fully integrated 5 GHz low-power electrostatic discharge (ESD)-protected low-noise amplifier (LNA) in 90 nm CMOS is presented. This 9 mW LNA, with a 1.2 volt supply voltage, features a 12 dB power gain and 3.4 dB noise figure, while maintaining an input return loss below -20 dB. The LNA is ESD protected up to 5.5 kV human body model (HBM) using an on-chip inductor and clamping diodes, implemented as "plug-and-play" components. To the authors' knowledge, this LNA achieves the highest ever-reported ESD protection level in any 90 nm RF CMOS technology.

The potential for low power RF systems on chip of a 90nm CMOS technology is demonstrated for the first time on a monolithic 5GHz low noise amplifier. This technology combines a portfolio of high Q passive components with high RF performances 70nm physical gate length NMOSFETs (200GHz f(max)-150GHz f(T)) presenting a ratio power gain/current gain higher than 1 up to the maximum measurement frequency.