This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the NAND Flash memory roadmap below the 20-nm technology node.

We propose a cell structure with monocrystalline floating gate and 6 nm to 8 nm of thermally grown SiO2 interpoly dielectric (IPD) for <;20 nm NAND Flash arrays. This thin IPD avoids the bitline pitch scaling barrier caused by the ONO thickness limitation. Simulations show that, down to the 12 nm node, such cells can be programmed without excessive IPD leakage. The combination of modeling and experimental results indicates that 12nm memory cells with 7 nm SiO2 IPD can achieve 10 years data retention.

It is shown that the performance impact of middle-of-line (MOL) patterning process variations can be reduced by 30% by relaxing the standard cell gate pitch by 10% in both 20nm bulk planar (BPL) and 14nm bulk finFET (BFF). Tungsten can safely replace copper in local interconnect IM2, which allows the MOL critical dimensions (CD) to be reduced by 40% in 20nm BPL, resulting in 5% performance improvement. In 14nm BFF, 10% performance degradation can be traded in for 40% smaller IM1 contact area, allowing for a cell silicon footprint benefit of up to 20%.

This work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration.

For the first time we demonstrate ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 nm with improved program performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacturability and scalability for high density memory application.

A transient leakage current was measured as a function of time for thin (~9 nm) strontium titanate (STO) capacitor dielectrics with RuOx as a bottom electrode and TiN as a top electrode at different temperatures under constant direct current (DC) bias stress. With the space-charge-limited (SCL) current theory, the mobility of oxygen vacancies (VO) and the activation energy (E0) of VO were extracted. By closely examining the time-zero current-voltage (I-V) curves for a positively and a negatively held DC bias conditions before and after the stresses, an understanding of trap-assisted-tunneling (TAT) current, initiated by oxygen vacancies (VO) is presented. Based on this understanding, a way to further reduce the leakage current for a sub-10 nm dielectric film is provided.

Highly scaled vertical cylindrical cell with 22nm diameter bi-layer poly-silicon channel for 3D NAND Flash memory is successfully developed. A thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole was introduced. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells. We also explore, what is the equivalent feature size (F-EQ) that can be reached by layer stacking, taking the inevitable process restrictions into consideration.

Metal-insulator-metal capacitors with SrxTiyOz (STO) dielectric films on TiN, Ru, and RuOx bottom electrodes with TiN top electrodes were studied. Metastable perovskite STO films with compositions in the Sr/(Sr+Ti)∼54–64 at. % range were obtained by crystallization at 600 °C in N2 of dielectric stacks grown by atomic layer deposition consisting of Sr-rich STO films [Sr/(Sr+Ti)∼64 at. %] on thin interfacial TiOx layers. The significant decrease in equivalent oxide thickness (EOT) and STO lattice parameter observed with increasing TiOx thickness indicates full intermixing of the TiOx and STO layers during the crystallization anneal, which results in the formation of an STO layer with higher Ti content and higher dielectric constant. The Sr-rich STO on TiOx stacks crystallize with small grain size, favorable for low leakage (JG). A significant improvement in JG for e-injection from the bottom electrode is obtained when using RuOx, as compared to TiN or Ru. A milder JG improvement with RuOx bottom electrode is also seen for e-injection from the top TiN electrode, indicating that higher quality perovskite STO films are formed on RuOx, or equivalently, that their trap density is lower. We propose oxygen scavenging from the STO by TiN or Ru electrodes, eliminated or reversed when using RuOx, as an explanation for the improvement. Using an optimized RuOx/TiOx/STO/TiN stack we obtained leakage of 10−7 A/cm2 (at 0.8 V) and 0.4 nm EOT.

A planar SONOS capacitor was used to optimize different parameters of the gate stack, in view of integration in a 3D cell. It is found that a poly-Si substrate strongly degrades the channel mobility but program and retention are not compromised. The ONO stack is found to scale down to 3/4/5nm for tunnel oxide/trapping nitride/blocking oxide, respectively. FUSI gate could be an interesting option to improve the erase operation.

A comparative study of the growth behavior of nm-thin ruthenium layers by plasma enhanced atomic layer deposition using two ruthenium precursors is discussed. For bis(ethylcyclopentadienyl)-ruthenium or Ru(EtCp)2, we have found a large incubation time on titanium nitride when using N2/NH3 plasma. With N2/H2 plasma the incubation was significantly reduced. For (methylcyclopentadienyl-pyrrolyl)ruthenium or MCPRu, no incubation was observed for either plasmas. The measured growth per cycle was ~ 0.02 nm for Ru(EtCp)2 whereas ~ 0.04 nm for MCPRu. The top surface of the PE-ALD Ru films can be oxidized without surface roughening by applying a low pressure O2 anneal, while O3 exposure leads to roughening due to etching and re-deposition downstream of etched Ru. Awareness of the impact of oxidizing ambients on Ru is essential for successful integration of Ru layers as electrode in metal-insulator-metal capacitors.

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F(2), with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

In this paper, we provide evaluation of memory stacks with La, Lu and Gd aluminates as charge trapping materials. Critical integration issues are pointed out, particularly the mixing of these materials with adjacent layers. It is found that, in order to control the mixing of the aluminates with the tunnel oxide, nitride (for Gd) or nitride + oxide (for La and Lu) buffer layers have to be used. The nitride buffer layer, however, mixes with the tunnel oxide during stack fabrication. This results in very good erase and endurance performance, which is attributed to enhanced hole tunneling from the Si substrate, but degrades the retention performance.

In this paper we compare a novel plasma-enhanced atomic layer deposition (PEALD) oxide with more conventional HTO and ISSG oxides. We show that, remarkably for a deposited oxide, the oxide quality is, both in terms of field-to-breakdown and SILC generation, comparable to that of ISSG thermal oxide. Finally, we show that data retention of SONOS stack with PEALD is significantly better than for stacks with ISSG tunnel oxide. PEALD oxide is, therefore, a promising choice for 3D non-volatile flash technologies.

Metastable perovskite SrxTiyOz (STO) films were formed over a wide composition range by crystallization of layers grown by atomic layer deposition. An expansion of the lattice, decrease in permittivity and mild increase in band gap are observed with increasing Sr content. Sr-rich films [Sr/(Sr+Ti)∼62 at. %] show significant improvement in leakage current at low equivalent oxide thicknesses (EOT) as compared to stoichiometric films (Sr/(Sr+Ti) ∼50 at. %). TiN/STO/TiN capacitors with leakage ∼10−6 A/cm2 at 1 V were obtained at 0.6 nm EOT for crystalline Sr-rich STO. The difference in leakage behavior was found to correlate with different microstructures developed during crystallization.

Flash pitch scaling will lead to cells for which the wordline no longer fits between the floating gates, which results in loss of sidewall coupling, causing unacceptable program saturation due to IPD leakage. We present a dual layer poly/metal floating gate (FG) memory device avoiding this saturation and demonstrate +4V programming above the fresh level in a fully planar cell without sidewall coupling using an Al2O3 IPD. The data retention at 200C and cycling performance up to 100k cycles are similar to cells with poly FG.

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiOx interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10−6 A/cm2 (10−8 A/cm2) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (> 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.