Scanning capacitance microscopy and electrostatic force microscopy have been used to characterize commercial semiconductor devices at various stages of the fabrication process. These methods, combined with conventional atomic force microscopy, allow to visualize qualitatively the oxide thickness, the nature of dopants and the exact position of implanted areas.

A large variety of physical analysis techniques are used in the semiconductor industry to identify defects impacting yield or reliability. Identification of a defect often requires the combined use of several techniques to give a clear understanding of the defect nature.In the present study, several microscopy techniques (SEM, TEM, Analytical-TEM, AFM and FIB) have been intensively used to identify the origin of residues observed on the edge of large active areas in a low power CMOS technology. A KLA automatic inspection system has been used for locating and quantifying the defects. It has been shown that the defects are related to amorphous silicon residues whose origin is related to the gate deposition process. In the process, the polysilicon gate is deposited in two steps. A first thin amorphous silicon layer is deposited, through which the Vt implant is done, followed by the deposition of a thick polysilicon layer.Analysis of defaults showed that the residues are related to a non-uniform thin oxide layer located between the thick polysilicon layer and the underlying thin amorphous silicon, which halts the polysilicon gate etch. Thicker native oxide on amorphous silicon due to humidity or drying spots is the presumed source of the thin non-uniform oxide. Increasing the HF dip before the polysilicon deposition eliminated almost all residues. No negative effect on the oxide quality or other electrical parameter has been observed. Eliminating altogether the amorphous-Si gate deposition process is an even more robust solution.

In this work the reliability of a 0.35 /spl mu/m p+ poly-gate pMOSFET CMOS technology under conductive channel hot carrier conditions is investigated. It is found that at any bias and temperature condition applied, the degradation of sufficiently short channel length (Leff/spl sime/0.14 um) devices results in a reduction in drive current due to the impact of donor type interface trap generation and positive charge formation during the stress. At these dimensions the degradation is controlled by a contribution of both Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) mechanism. We will show the role that each of these two mechanisms play in determining the shift of typical device parameters. A methodology to decouple the two effects is also provided allowing to quantify each contribution separately at any bias and temperature condition. A conductive CHC model that takes into account the impact of both mechanisms to the device lifetime at the worst observed degradation condition (Vg=Vd) is also discussed.

We demonstrate a 0.08 /spl mu/m CMOS suitable for high-performance (V/sub dd/=1.8 V) and low-power applications (V/sub dd/<1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for L/sub eff/ down to 0.06 /spl mu/m in the NFET and 0.08 /spl mu/m in the PFET. Aggressive lateral and vertical dopant engineering allow the VT to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at V/sub dd/=1 V over the regular-V/sub T/ process.

Plasma charging causes gate oxide degradation and breakdown. In this paper a mechanisin is presented for P+ poly gates where the plasma charging during processing causes a stress induced Ieakage behavior (SILC) under accelerated life testing. The mechanism appears under positive gate bias for P+ poly-gated devices, and does not show under any bias conditions for N + poly-gated devices. The degradation exhibited a strong dependence on oxide thickness and temperature. The mechanism is explained in terms of enhanced degradation for the P+ poly-gated devices during processing and subsequent trap assisted-tunneling under accelerated life test.

Deep-submicron CMOS is the primary technology for ULSI systems. Currently, the state-of-the-art CMOS device has a 0.25-mu m effective channel length and operates at 2.5 V. As the CMOS technology is extended into the deep submicron range, it is estimated that the next generation will have a nominal channel length of 0.15 mu m with a supply voltage of less than or equal to 2 V. In this paper, two potential technologies with application to 1.X-V CMOS are presented. First, a bulk CMOS technology with the nominal channel length of 0.15 mu m is described. It is next argued that because of issues related to power dissipation, such a device may face problems when operated at its maximum speed-density potential in highperformance logic chips. CMOS on a silicon-on-insulator (SOI) substrate offers circuits with lower power at the same performance. Such a CMOS technology, with channel lengths down to less than 0.1 mu m, is described next. This technology is particularly useful for applications near a 1.0-V supply. We describe, for example, a 512Kb SRAM with an access time of less than 3.5 ns at 1.X V. The clear power-performance advantage of CMOS on SOI over that of CMOS on bulk silicon in the 1.X-V regime makes it the technology of choice for sub-0.25-mu m CMOS generations.

Electron and hole current densities across the gate oxide layer of MOSFETs due to Fowler-Nordheim tunneling are calculated by employing the well-known two-dimensional device simulator FIELDAY. The parametric dependences of these currents on, for example, electric field across the oxide layer, effective masses of electrons and holes, and barrier heights are studied in some detail. Calculated gate currents due to tunneling, as functions of drain-source voltage and gate-source voltage, are compared with available experiments. The agreement between the theory and experiments appears encouraging.

An integrated 0.35 /spl mu/m CMOS technology with 0.15 /spl mu/m effective channel length (L/sub EFF/) is demonstrated in a 200 mm line. X-ray lithography is used for the critical gate level, along with conventional deep-UV and mid-UV lithography for other levels. Shallow Trench Isolation (STI) is used to achieve 0.35 /spl mu/m design rules. The NFET and PFET devices are designed for operation with a scaled power supply of 1.8 V. This technology provides 50% performance improvement relative to a 2.5 V, 0.5 /spl mu/m design rule, 0.25 /spl mu/m L/sub EFF/ high-performance CMOS technology.<>

A process for depositing in-situ very-thin (<10 nm) SiO/sub 2/ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO/sub 2/ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm/sup 2/ at J=0.1 A/cm/sup 2/. The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices.< >

In this paper a CMOs technology with the nominal channel length of 0.15 Am and minimum channel length below 0.1 /spl mu/m is presented. Loaded NAND (FI=FO=3, CL=240 fF) delay of 200 psec and unloaded delay of 33 psec at supply voltage of 1.8 V is demonstrated. In order to minimize short channel effects down to channel length below 0.1 /spl mu/m, highly non-uniform channel doping obtained by indium and antimony, and source-drain extensions were utilized. To minimze the gate RC, a polycide s stack gate structure was used.

Boron is found to segregate readily from the channel region into the arsenic implanted source/drain regions during the As activation anneal. The resulting boron depletion around the source and drain locally lowers the surface potential required for inversion and contributes substantially to the V(T) rolloff and drain-induced barrier lowering (DIBL) in subquarter-micrometer NMOSFET's. This boron redistribution originates from the As implantation damage in the source and drain regions.

Very-high-transconductance 0.1 mu m surface-channel pMOSFET devices are fabricated with p/sup +/-poly gate on 35 AA-thick gate oxide. A 600 AA-deep p/sup +/ source-drain extension is used with self-aligned TiSi/sub 2/ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices.<>

X-ray lithography introduces device radiation damage from the high energy photons during the lithography process. We have studied this effect on deep submicron n- and p-channel MOSFETs with gate dielectric thickness at 7 to 13 nm. After the x-ray irradiation the device characteristics are strongly affected by the generation of oxide charges, interface states and electron traps. These introduced damages cause the reduction of device transconductance, shift of the threshold voltages and increased leakage current. However, this degradation of device and circuit is lessened from technology scaling by thinning the gate oxide and lowering the supply voltage. The x-ray radiation damage induces interface states and oxide charges which can be annealed out with a low temperature (400°C) forming gas (FG, 90% N2, 10% H2) annealing process. The device properties are essential unchanged after the annealing process. However, the residue damage is shown to enhance hot-carrier instability of p-channel devices if the remaining neutral traps act as electron or hole traps in the SiO2. In this paper, we investigate the radiation effects on the n- and p-channel MOSFETS fabricated with deep submicron device processes with thinner gate oxides and compare the hot carrier reliability of these devices after the synchrotron x-ray irradiation and also after the post metal forming gas annealing. The results indicate the device hot carrier instability has no effect on the devices with thin gate oxide with thickness approaching the electron tunneling range.

Enclosed-layout transistors fabricated in standard CMOS processes are known to offer a natural robustness against radiation effects, a characteristic which is boosted in submicron technologies due to the reduction of the oxide thickness. In this paper, a thorough analytical I–V model of short-channel polygonal enclosed-layout transistors is proposed, addressing the issues of drain-induced barrier lowering and threshold voltage roll-off due to short-channel effects. Experimental data is reported, showing good agreement with the theoretical model.

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.< >

Growth of rough polycrystalline silicon films has been achieved on SiO2 surfaces over a broad temperature range (≥100 °C) using SiH4 chemical vapor deposition at low pressures (mTorr range), with smaller grain structure and roughness length scale achieved at lower temperatures. Rough morphology over a broad temperature range is attributed to the combination of nucleation-controlled initial growth (on SiO2) and domination of growth by surface reaction (cf. gas phase).

The accumulation mode devices used in this experiment were presented in detail in a previous paper [2]. They were made in a 0.5pm CMOS on SO1 technology, with a lOOnm thick silicon, 12.5nm gate oxide and a reverse gate type compared to the source/drain doping. For purpose of comparison, enhancement mode devices made in a similar CMOS technology were used. Figure 1 shows the output characteristics of Lmask70.8pm (a) n- and (b) pchannel MOSFET. The accumulation devices show a reduced effect of impact ionization close to the drain, which allows them to operate at higher drain voltages [a]. Because of this reduced drain electric field, hot-carrier reliability of accumulation mode MOSFETs is improved, as shown in figure 2 for the case of the n-channel MOSFET. In both devices the maximum degradation occurs close to the threshold voltage, contrary to the case of the bulk device, where the maximum degradation occurs at a point of maximum substrate current. The strong degradation at VG close to V, is due to the hot-hole injection close to the avalanche breakdown of the drain junction [3]. Since the breakdown voltage decreases when the gate voltage increases, as can be seen on figure 2, hot-carrier generation and its effects are also reduced. Figure 3 shows that enhancement mode pchannel devices have a better reliability than accumulation mode devices, in spite of the fact that both types of devices were stressed at the same peak gate current (fig. 3). In both devices the drain current and the threshold voltage vary similarly, indicating that the degradation mechanism are similar. Figure 4 details the variation of the subthreshold characteristics of the accumulation mode device. The I,(VG) characteristics is shifted due to electron trapping, and the short channel behavior of the device is degraded (the difference between the characteristics at high and low drain voltage is increased after stress). This and the increase of the drain current in strong inversion (fig. 4) indicate that the device is shortened, due to electron trapping, similarly to the case of bulk pchannel MOSFETs. The increased degradation of the accumulation mode device is due to the degraded short-channel behavior of accumulation mode devices, which was already observed in bulk p-channel buried channel devices [4]. However, the accumulation mode device requires a higher drain voltage than the enhancement mode devices -at a given gate current, so that at a given drain voltage it’s reliability is still comparable to that of an enhancement mode device. Furthermore, at drain voltages comparable to those in the n-channel MOSFET, the degradation of the pchannel device is negligible, so that the overall reliability of an accumulation mode CMOS circuit is not affected by the increased degradation of the p-channel device.

When a high dose of As is implanted (e.g., 25 keV, 3×1015 cm−2) into B-doped Si and the sample is subsequently annealed at 900 °C/5 min, pronounced segregation of the B into the implanted region occurs. This creates a B-depleted region beyond the As profile. It is demonstrated that the B segregation is driven primarily by the implantation induced damage rather than by As-B chemical and/or by electric field effects. The B segregation is nearly complete after a relatively low temperature (≲600 °C/30 min) anneal. Two-dimensional device simulations show that the B depletion observed here can account for ≂50 mV threshold voltage roll off (at a drain bias of 0.1 V) in a Si metal–oxide–semiconductor field effect transistor of 0.2 μm gate length.

The experimentally observed V/sub T/ roll-off and Drain Induced Barrier Lowering (DIBL) at channel lengths of approximately=0.2 mu m in Si-MOSFETs is underestimated by conventional 2D numerical simulations. In this paper it is shown that this is due to B segregation from the channel region towards the As-implanted source/drain regions during the As activation anneal. The resulting B depletion close to the source and drain lowers the local V/sub T/ and contributes significantly (up to 50% in 0.2 mu m n-channel MOSFETs) to the V/sub T/ roll-off and DIBL in sub-quarter micron NMOSFETs. This B redistribution originates mainly from ion implantation damage in the source and drain.<>