This paper highlights the challenges and solutions associated with forming backside source/drain (S/D) contact with low contact resistivity (RhoC). The backside nanosecond laser anneal (NLA) process window is identified by thermal simulation and experimental verification of resistance and reliability impact on the frontside Cu-based back-end-of-line (BEOL). Optimal NLA energy dose (ED) is implemented on nanosheet transistors achieving low RhoC backside contact.

Phase change memory (PCM) is considered an enabling technology for non-volatile multilevel data storage and neuromorphic computing. Recent advancements in PCM have highlighted the need to improve resistance drift and energy efficiency. At present, binary alloys that phase-separate upon crystallization offer a promising solution. The Al–Sb binary alloy crystallizes into a rhombohedral Sb-rich phase and a cubic AlSb phase, with the latter having a higher melting temperature that enables selective melting of the Sb-rich phase for partial RESET programming. Continuum resistance states result from a reversible alloying process, in which programming pulses modulate the granularity and aluminum content of the amorphous Sb-rich phase. Al0.4–Sb0.6 PCM cells, fabricated on Si-foundry templates, exhibit a high resistance contrast of up to 4000× between fully amorphous and crystalline states, along with a low resistance drift coefficient (∼0.06). The high melting point of AlSb also leads to nanoscale compositional heterogeneity, which persists in the amorphous state, suppressing structural relaxation and thus reducing resistance drift. These findings position Al0.4–Sb0.6 as a promising material for engineering multilevel PCM cells based on phase-separating alloys.

Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of co-optimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge.

This paper examines various approaches for integrating backside power distribution network (BSPDN) with nanosheet transistor technologies. Deep Trench Via (DTV) based BSPDN schemes, except for Shifted Frontside Via Backside Power rail (SFVBP), do not offer cell level scaling benefits, but via resistance of SFVBP could remain a bottleneck. Direct Backside Contact (DBC) based schemes offer best cell level scaling. A novel self-aligned backside contact (SABC) scheme integrated with nanosheet transistors is demonstrated with immunity to misalignments in backside contact formation. The structure exhibits good device characteristics and satisfactory reliability.

Semiconductor industry transitions from the era of planar FETs to the era of three-dimensional (3D) transistors greatly improving performance per footprint. In planar FETs, the gate width W G , the lateral source/drain (S/D) size, and the metallic contact width W C are all equal to the transistor width W. FinFETs feature a 3D channel geometry where the gate perimeter W G per fin or, equivalently, the effective channel width W eff is significantly larger than the fin pitch P that defines the S/D and metallic contact width per fin (Fig. 1). Large W eff reduces the channel resistance but small P increases the parasitic external resistance R EXT making it a performance limiting factor. Innovative processes and new materials are required for reducing components of R EXT thereby realizing FinFET performance advantage. This work explores millisecond and nanosecond laser annealing techniques for reducing FinFET R EXT focusing on source/drain and contact resistances. Transistor-level specific contact resistivity in sub 10 -9 Ω-cm 2 range has been achieved for both nFETs and pFETs with corresponding improvements in R EXT and switching currents.

Models of artificial intelligence (AI) that have billions of parameters can achieve high accuracy across a range of tasks 1 , 2 , but they exacerbate the poor energy efficiency of conventional general-purpose processors, such as graphics processing units or central processing units. Analog in-memory computing (analog-AI) 3 – 7 can provide better energy efficiency by performing matrix–vector multiplications in parallel on ‘memory tiles’. However, analog-AI has yet to demonstrate software-equivalent (SW eq ) accuracy on models that require many such tiles and efficient communication of neural-network activations between the tiles. Here we present an analog-AI chip that combines 35 million phase-change memory devices across 34 tiles, massively parallel inter-tile communication and analog, low-power peripheral circuitry that can achieve up to 12.4 tera-operations per second per watt (TOPS/W) chip-sustained performance. We demonstrate fully end-to-end SW eq accuracy for a small keyword-spotting network and near-SW eq accuracy on the much larger MLPerf 8 recurrent neural-network transducer (RNNT), with more than 45 million weights mapped onto more than 140 million phase-change memory devices across five chips.

Tellurium-free antimony-based phase change memory (PCM) alloys have attracted much attention due to their superior attributes such as fast switching speed, wide resistance window, and low drift. However, programming reproducible intermediate states in such PCM materials has been challenging. In this study, bilayer PCM cells comprised of Ga–Sb films with two different compositions separated by a 1-nm-thick AlO x diffusion barrier layer were fabricated on Si foundry templates with a Ø120-nm TiN heater and TaN top contact. The current–voltage measurements of the cells exhibit two threshold voltages, separating three stable resistance regions. These cells can be controllably switched among three resistance states, that is, the SET ( $\sim 10^{3} \ \Omega)$ , intermediate ( $\sim 10^{4} \ \Omega)$ , and RESET states ( $\sim 5\times 10^{5}\,\,\ \Omega {)}$ . The phase transitions during switching among three resistance states are discussed and correlated with the device resistance profiles. The stability of the AlO x barrier layer is investigated with transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDS).

The need to repeatedly shuttle around synaptic weight values from memory to processing units has been a key source of energy inefficiency associated with hardware implementation of artificial neural networks. Analog in-memory computing (AIMC) with spatially instantiated synaptic weights holds high promise to overcome this challenge, by performing matrix-vector multiplications (MVMs) directly within the network weights stored on a chip to execute an inference workload. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and communication to move towards configurations in which a full inference workload is realized entirely on-chip. Moreover, it is highly desirable to achieve high MVM and inference accuracy without application-wise re-tuning of the chip. Here, we present a multi-core AIMC chip designed and fabricated in 14-nm complementary metal-oxide-semiconductor (CMOS) technology with backend-integrated phase-change memory (PCM). The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and processing involved in ResNet convolutional neural networks and long short-term memory (LSTM) networks. We demonstrate near software-equivalent inference accuracy with ResNet and LSTM networks while implementing all the computations associated with the weight layers and the activation functions on-chip. The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS/W for 8-bit input/output matrix-vector multiplications.

We discuss the process challenges such as the heater geometry effect, heater patterning processes and deep via formation. Based on the electrical data, we improve the processes and Phase Change memory (PCM) resistance distribution to meet Analog Computing requirement.

Analog non-volatile memory (NVM)-based accelerators for deep neural networks implement multiply-accumulate (MAC) operations – in parallel, on large arrays of resistive devices – by using Ohm’s law and Kirchhoff’s current law. By completely avoiding weight motion, such fully weight-stationary systems can offer a unique combination of low latency, high throughput, and high energy-efficiency (e.g., high TeraOPS/W). Yet since most Deep Neural Networks (DNNs) require only modest (e.g., 4-bit) precision in synaptic operations, such systems can still deliver “software-equivalent” accuracies on a wide range of models. We describe a 14-nm inference chip, comprising multiple 512×512 arrays of Phase Change Memory (PCM) devices, which can deliver software-equivalent inference accuracy for MNIST handwritten-digit recognition and recurrent LSTM benchmarks, and discuss various PCM challenges such as conductance drift and noise.

Achieving sufficient compute precision in matrix-vector multiply (MVM) operations is a key challenge for analog in-memory computing (AIMC) that relies on resistive memory devices. A device-level concept that addresses this challenge is that of projected-type phase-change memory (Proj-PCM). Here we present Proj-PCM devices based on carbon-based projection layer (CPL). We integrated these devices onto multi-tile AIMC chips fabricated in 14nm CMOS technology. CPL is shown to exhibit superior compatibility with the phase-change material layer (PCML) as well as the BEOL process. CPL also provides sufficient tunability of resistance window. The compute tiles with CPL-based Proj-PCM are shown to achieve higher computational precision compared to those with standard PCM devices.

Accurate programming of non-volatile memory (NVM) devices in analog in-memory computing (AIMC) cores is critical to achieve high matrix-vector multiplication (MVM) accuracy during deep learning inference workloads. In this paper, we propose a novel programming approach that directly minimizes the MVM error by performing stochastic gradient descent optimization with synthetic random input data. The MVM error is significantly reduced compared to the conventional unit-cell by unit-cell iterative programming. We demonstrate that the optimal hyperparameters in our method are agnostic to the weights being programmed, enabling large-scale deployment across multiple AIMC cores without further fine tuning. It also eliminates the need for high-resolution analog to digital converters (ADCs) to decipher the small unit-cell conductance during programming. We experimentally validate this approach by demonstrating an inference accuracy increase of 1.26% on ResNet-9. The experiments were performed using phase change memory (PCM)-based AIMC cores fabricated in 14nm CMOS technology.

Phase change memory (PCM) is one of the most promising candidates for non‐von Neumann based analog in‐memory computing–particularly for inference of previously‐trained deep neural networks (DNN). It is shown that PCM electrical properties can be tuned systematically using a projection liner, which is designed for resistance drift mitigation, in the manufacturable mushroom PCM. A systematic study of the electrical properties‐including resistance values, memory window, resistance drift, read noise, and their impact on the accuracy of large neural networks of various types and with tens of millions of weights is performed. It is sown that the DNN accuracy can be improved by the PCM with liner for both the short term and long term after programming, due to reduced resistance drift and read noise, respectively, despite the trade‐off of reduced memory window. The liner conductance, PCM device characteristics, and network inference accuracy with PCM memory window and reset state conductance is correlated, which allows us to identify the device optimization space to achieve better short term and long term accuracy for large neural networks.

Among the emerging approaches for deep learning acceleration, compute-in-memory (CIM) in crossbar arrays, in conjunction with optimized digital computation and communication, is attractive for achieving high execution speeds and energy efficiency. Analog phase-change memory (PCM) is particularly promising for this purpose. However, resistance typically drifts, which can degrade deep learning accuracy over time. Herein, we first discuss drift and noise mitigation by integrating projection liners into analog mushroom-type PCM devices, as well as tradeoffs with dynamic range. We then study their impact on inference accuracy for the Transformer-based language model BERT. We find that accuracy loss after extended drift can be minimal with an optimized mapping of weights to cells comprising two pairs of liner PCM devices of varying significance. Finally, we address the impact of drift on energy consumption during inference through a combination of drift, circuit, and architecture simulations. For a range of typical drift coefficients, we show that the peak vector-matrix multiplication (VMM) energy efficiency of a recently proposed heterogeneous CIM accelerator in 14 nm technology can increase by 3% to 15% over the course of one day to ten years. For convolutional neural network (CNN), long short-term memory (LSTM) and Transformer benchmarks, the increase in sustained energy efficiency remains below 10%, being greatest for models dominated by analog computation. Longer VMM integration times increase the energy impact of drift.

Analog in- memory computing (AIMC) using memristive devices is considered a promising Non-von Neumann approach for deep learning (DL) inference tasks. However, inaccuracies in the programming of devices, that are attributed to conductance variations, pose a key challenge toward achieving sufficient compute precision for DL inference. Fortunately, conduction variations in memristive devices, such as phase-change memory (PCM) devices, exhibit a strong state dependence. This state dependence can be exploited in synaptic unit cells that comprise more than one memristive device, to encode positive or negative weights. In such multi-memristive unit cells, we propose a method that optimally maps the weights to the device conductance values, by maximizing the number of devices at the stable SET and RESET states. We demonstrate that this method reduces the matrix-vector multiplication (MVM) error and is more resilient to non-ideal device retention characteristics. With this approach, we increase the mean experimental inference accuracy of a network trained for MNIST classification by 0.71% on two PCM-based AIMC cores, and the hardware-realistic simulated top-1 accuracy of a network trained for ImageNet classification by 0.28%, while significantly reducing variability across multiple experiment instances.

Continually learning new classes from few training examples without forgetting previous old classes demands a flexible architecture with an inevitably growing portion of storage, in which new examples and classes can be incrementally stored and efficiently retrieved. One viable architectural solution is to tightly couple a stationary deep neural network to a dynamically evolving explicit memory (EM). As the centerpiece of this architecture, we propose an EM unit that leverages energy-efficient in-memory compute (IMC) cores during the course of continual learning operations. We demonstrate for the first time how the EM unit can physically superpose multiple training examples, expand to accommodate unseen classes, and perform similarity search during inference, using operations on an IMC core based on phase-change memory (PCM). Specifically, the physical superposition of few encoded training examples is realized via in-situ progressive crystallization of PCM devices. The classification accuracy achieved on the IMC core remains within a range of 1.28%-2.5% compared to that of the state-of-the-art full-precision baseline software model on both the CIFAR-100 and miniImageNet datasets when continually learning 40 novel classes (from only five examples per class) on top of 60 old classes.

The precise programming of crossbar arrays of unit-cells is crucial for obtaining high matrix-vector-multiplication (MVM) accuracy in analog in-memory computing (AIMC) cores. We propose a radically different approach based on directly minimizing the MVM error using gradient descent with synthetic random input data. Our method significantly reduces the MVM error compared with conventional unit-cell by unit-cell iterative programming. It also eliminates the need for high-resolution analog-to-digital converters (ADCs) to read the small unit-cell conductance during programming. Our method improves the experimental inference accuracy of ResNet-9 implemented on two phase-change memory (PCM)-based AIMC cores by 1.26%.

Material properties of Ga–Sb binary alloy thin films deposited under ultra-high vacuum conditions were studied for analog phase change memory (PCM) applications. Crystallization of this alloy was shown to occur in the temperature range of 180–264 °C, with activation energy >2.5 eV depending on the composition. X-ray diffraction (XRD) studies showed phase separation upon crystallization into two phases, Ga-doped A7 antimony and cubic zinc-blende GaSb. Synchrotron in situ XRD analysis revealed that crystallization into the A7 phase is accompanied by Ga out-diffusion from the grains. X-ray absorption fine structure studies of the local structure of these alloys demonstrated a bond length decrease with a stable coordination number of 4 upon amorphous-to-crystalline phase transformation. Mushroom cell structures built with Ga–Sb alloys on ø110 nm TiN heater show a phase change material resistance switching behavior with resistance ratio >100 under electrical pulse measurements. TEM and Energy Dispersive Spectroscopy (EDS) studies of the Ga–Sb cells after ∼100 switching cycles revealed that partial SET or intermediate resistance states are attained by the variation of the grain size of the material as well as the Ga content in the A7 phase. A mechanism for a reversible composition control is proposed for analog cell performance. These results indicate that Te-free Ga–Sb binary alloys are potential candidates for analog PCM applications.