Here we present a highly scalable reconfigurable field effect transistor concept, which is capable of dynamically switching between p-type, n-type, and ambipolar operation modes by adaptively changing the applied back-bias. The devices are processed on full-scale 300 mm wafers and reach gate lengths down to 20 nm, integrable into a 22 nm FDSOI platform with only minor process modifications. We demonstrate symmetric IV characteristics of p- and n-program with $I_{ON}/I_{OFF}$ ratio up to 103 at a $V_{DD}$ of 0.8 V, and propose an exploitation in hardware security. In ambipolar mode, frequency multiplication requiring only a single transistor is experimentally demonstrated.

This paper presents 22FDSOI device RF performance figure of merit dependencies on the design parameters, such as gate length, width per finger, number of fingers, centerline poly pitch, as well as the vertical gate repetition. With a proper design parameters combination, the device can achieve as high as 413 GHz of $f_{MAX}$. As a circuit demonstration, a 2-stage 2-stack power amplifier achieves an output power of 20.2 dBm and 32 % peak PAE at 28 GHz.

In this work, we study and characterize the layout-induced device strain and its impact on RF performance of 22-nm-ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FDSOI) P-channel field-effect transistor (PFET). This will help in boosting and optimizing the RF performance for the targeted application. With shrinking device dimensions, conventional stress liners and embedded stressors used in strain-engineered CMOS devices become less effective. Therefore, intrinsically strained materials, such as compressively strained SiGe, are widely used to boost the holes' mobility in the channel. The stress level depends on both the manufacturing process and device geometry, and the optimization of these leads to improved dc and RF performances of PFET devices. We hereby study various layout parameters, such as width and length of the active region, contacted poly pitch, number of fingers, and source/drain contact, to maximize the channel uniaxial strain parallel to the current flow direction and, thus, improve the electrical performances. The studied layout parameters are then applied on sliced-active (RX) structures, which enables to achieve up to 30% improvement of both f T and f MAX parameters of SiGe PFET with respect to a reference device. This also allows reducing the parasitic capacitance without significantly degrading the dc performance. The device strain modeling and physical characterization were conducted through the finite-element method (FEM) and nanobeam electron diffraction (NBED) in the transmission electron microscopy (TEM), respectively.

The microstructure of ferroelectric hafnium oxide plays a vital role for its application, e.g., non-volatile memories. In this study, transmission Kikuchi diffraction and scanning transmission electron microscopy STEM techniques are used to compare the crystallographic phase and orientation of Si and Zr doped HfO2 thin films as well as integrated in a 22 nm fully-depleted silicon-on-insulator (FDSOI) ferroelectric field effect transistor (FeFET). Both HfO2 films showed a predominately orthorhombic phase in accordance with electrical measurements and X-ray diffraction XRD data. Furthermore, a stronger texture is found for the microstructure of the Si doped HfO2 (HSO) thin film, which is attributed to stress conditions inside the film stack during crystallization. For the HSO thin film fabricated in a metal-oxide-semiconductor (MOS) like structure, a different microstructure, with no apparent texture as well as a different fraction of orthorhombic phase is observed. The 22 nm FDSOI FeFET showed an orthorhombic phase for the HSO layer, as well as an out-of-plane texture of the [111]-axis, which is preferable for the application as non-volatile memory.

With the discovery of ferroelectricity in HfO 2 based thin films and the co-integration of ferroelectric field effect transistors (FeFET) into standard high-k metal gate (HKMG) CMOS platforms, the FeFET has emerged from a theoretical dream to an applicable reality. This paper summarizes the status of GLOBALFOUNDRIES FeFET technology and some of its potential applications. We show excellent 0.12µm 2 SRAM yields of our mature 28nm CMOS platform, with co-integrated FeFETs, exhibiting a solid memory window of 1.4V. In contrast to conventional embedded memory cells, the FeFET can be integrated like a regular 26Å EOT transistor, exhibiting two reversibly programmable VT states, while offering full design flexibility. We show state of the art across wafer VT variability of the programmed and erased states of the FeFETs and discuss its layout-dependence. Embedded size-competitive FeFETs already allow solid separation of the memory states, approaching a mature 6Sigma distribution. Reasonable endurance and stable data retention are demonstrated. Moreover, an outlook of this technology beyond the von Neumann computing will be discussed, considering some of the various applications of this new, versatile device.

Recently, a 22nm fully depleted gate-first SOI technology (FDSOI) has shown significant promise as a low-cost alternative to FinFETs with devices that are tunable between low-leakage and high-performance regimes. [1] The 22nm FDSOI PFET utilizes a SiGe channel with epitaxial grown raised source/drain (RSD) to define the junction profile, strain the channel, and facilitate contact formation. The pRSD epitaxial growth is typically a two-layer process with a main layer of SiGe:B followed by a capping layer of Si. Because the RSD epitaxy grows along the spacer dielectric, it results in a parasitic capacitance to the Gate electrode which then contributes to the total MOSFET capacitance and degrades AC device performance. Since the thickness of the main layer as well as the cap layer has a strong influence on this parasitic capacitance (Cgd), the RSD thickness should, in theory, be kept as low as possible. This is necessary to achieve the maximum AC and RF device performance. However, decreasing the RSD thickness below a certain level has the undesirable effect of DC performance drop. Therefore, another approach is needed to decrease Cgd further without degrading the drive current. In this paper we present one of the strongest methods to increase FDSOI technology AC/RF device performance, namely faceted raised source/drain epitaxial growth. Faceted pRSD epitaxy effectively decouples the RSD height and Cgd, lowering the parasitic capacitance not by reduced total RSD height, but rather by eliminating the shared wall between the Gate and the RSD. This simple approach has two desirable outcomes: 1) low Cgd & AC performance gain, and 2) low electrical variability via suppressing the influence of RSD height variation. The primary electrical response from faceted pRSD is the lowering of Cgd up to 25% at matched DC performance at zero gate bias; and this resulted in approximately 5% ring oscillator performance and ca. 20GHz RF p-Ft improvement. Other advantages of faceted pRSD are the selectivity in epitaxial growth and electrical variability. As mentioned previously, in a typical FDX device, RSD height needs to be controlled very tightly to achieve low device variability in DC transistor parameters (Ieff, Vtsat, Ioff) and Cgd. With faceted pRSD, however, this “shared wall” between Gate and RSD is liminated. We observed that the Cgd did not respond over a range of +/- 13% in main layer thickness, which led to a tight distribution of transistor parameters. Put another way, with faceted RSD, the primary need of a tight control over the pRSD thickness is eliminated. References [1] R. Carter and et al., "22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications," in IEDM16, San Fransisco, 2016.

As operating frequency and circuit density of VLSI systems continue to increase, the L*di/dt induced voltage fluctuations in the power grid increasingly becomes a source of voltage/timing problems. On-chip decoupling capacitors, placed in close proximity to the power grid conductors, can offset parasitic inductances and thereby reduce the high frequency noise. High capacitance density MIM capacitors, placed between the last two metal layers, have been shown to be effective in achieving on-chip decoupling in high performance processors. There have been many reports in the literature on the use of high-k material such as Ta 2 O 5 , HfO 2 , ZrO 2 for MIM capacitors [1-5]. A large number of reports of high-k MIM are focused on DRAM rather than decoupling capacitors applications [2-4]. One important difference between the DRAM capacitor module and decoupling capacitors is the thermal budget requirement. DRAM capacitors allow a higher thermal budget (~700°C) compared to embedded decoupling capacitors which must meet the BEOL thermal budget requirement (~400°C). We have recently reported an improved reliability by addition of Al into ZrO 2 [6]. In this work, we report detailed material, electrical and further reliability characterization of ZrO 2 -based MIM capacitor capable of meeting stringent reliability requirement while maintaining compatibility with the backend processing thermal budget. A capacitor with >20fF/μm 2 capacitance density and leakage current density <;100nA/cm 2 meeting lifetime target (operated on both polarities) is demonstrated.

Cobalt oxide (CoO) films are grown epitaxially on Si(001) by atomic layer deposition (ALD) using a thin (1.6 nm) buffer layer of strontium titanate (STO) grown by molecular beam epitaxy. The ALD growth of CoO films is done at low temperature (170–180 °C), using cobalt bis(diisopropylacetamidinate) and water as co-reactants. Reflection high-energy electron diffraction, X-ray diffraction, and cross-sectional scanning transmission electron microscopy are performed to characterize the crystalline structure of the films. The CoO films are found to be crystalline as-deposited even at the low growth temperature with no evidence of Co diffusion into Si. The STO-buffered Si (001) is used as a template for ALD growth of relatively thicker epitaxial STO and TiO2 films. Epitaxial and polycrystalline CoO films are then grown by ALD on the STO and TiO2 layers, respectively, creating thin-film heterostructures for photoelectrochemical testing. Both types of heterostructures, CoO/STO/Si and CoO/TiO2/STO/Si, demonstrate water photooxidation activity under visible light illumination. In-situ X-ray photoelectron spectroscopy is used to measure the band alignment of the two heterojunctions, CoO/STO and CoO/TiO2. The experimental band alignment is compared to electronic structure calculations using density functional theory.

With the introduction of 65 nm technology, the cross-sectional dimensions of copper interconnect in some layers are now smaller than 100 nm, which translates to current densities on the order of several MA/cm2. Electromigration as a root cause for chip failure is thus a major concern and is still being examined. In this article, the authors present recent failure analysis studies on metal-coated copper interconnects, using OBIRCH techniques in combination with FIB cross-sectioning and SEM and TEM imaging.