Computing-in-memory (CIM) based on analog resistive random access memory (RRAM) emerges as an energy-efficient technology for edge artificial intelligence (AI), where a large amount of ON-chip data buffer is needed to implement complex neural networks. In this work, we report a novel InGaZnO $_{\textit{x}}$ (IGZO)/carbon nanotube (CNT) hybrid-polarity 2T0C DRAM as a backend-of-the-line (BEOL) compatible buffer, which is a monolithic 3-D (M3D) integrated with HfO $_{\text{2}}$ -based analog RRAM array and Si CMOS logic to demonstrate a M3D-BRIC chip. The structural integrity and proper function of each layer are systematically verified. In particular, by incorporating n-type ultralow leakage IGZO field-effect transistor (FET) for write transistor and p-type high-current CNT-FET for read, this unique hybrid-polarity 2T0C design achieves a decent retention and desirably large read currents. It also helps enhance the effective sensing window and, more importantly, resolve the charge injection issue via counteractive coupling. To demonstrate the computational advantage of M3D-BRIC architecture, a typical high-resolution (Hi-Res) video processing task is further implemented using the YOLOv3 network for object detection. The benchmark shows that the M3D-BRIC chip with BEOL 2T0C DRAM could achieve a 48.25 x higher processing capability compared to its 2-D counterpart.

Near-Sensor Computing In article number 2302658, Jianshi Tang and co-workers demonstrate a prototype M3D-SAIL chip for energy-efficient near-sensor computing by monolithic three-dimensional integration of an IGZO-FET based photosensor array, an analog RRAM-based computing-in-memory array, and Si CMOS logic circuits. A video keyframe-extraction task is implemented, achieving a high classification accuracy of 96.7% and 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart.

In this work, we demonstrate a novel backend-of-the-line (BEOL) compatible IGZO/CNT hybrid-polarity 2T0C DRAM cell, which is further integrated on our analog RRAM-based monolithic 3D (M3D) integration platform for edge artificial intelligence (AI) applications. Incorporating n-type ultra-low-leakage InGaZnO x (IGZO) for write transistor and p-type high-current carbon nanotubes (CNTs) for read transistor, this design achieves a decent retention and desirably large read currents with a VLSI-compatible low data voltage (V data ). In addition, the unique IGZO-NFET/CNT-PFET hybrid-polarity 2T0C design enhances the effective sensing window and, more importantly, addresses the charge injection issue through counteractive coupling. This BEOL hybrid 2T0C cell achieves a long retention of 170s, a write speed of sub-20 ns and a read current of 29.7 μA/μm at V DS =1V with |V data | = 0.5V. The performance evaluation enables its utilization as a buffer layer on top of the computing-in-memory (CIM) layer with HfO 2 -based analog RRAM, empowering a prototype monolithic 3D chip (namely M3D-BRIC) for high-resolution (Hi-Res) videos processing. A YOLOv3 network is further implemented for the objects detection task, and the benchmarks show that the M3D-BRIC architecture of CIM/2T0C-DRAM could achieve a 48.25× higher processing capability than its 2D counterpart.

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlO x -based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta 2 O 5 -based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

The computing-in-memory (CIM) technology effectively addresses the bottleneck of data movement in traditional von-Neumann architecture, especially for deep neural network (DNN) acceleration. However, with the improving performance and parallelism of CIM processing elements (PEs), the substantial latency and power overhead caused by high-density intermediate results transmission has become a new bottleneck in CIM architectures. In this paper, we propose a spatial-designed CIM architecture based on the emerging Monolithic 3D (M3D) technology, and a spatiality-aware DNN mapping method for high-performance CIM systems. The proposed architecture introduces a novel hierarchy by implementing staggered tiers, enabling PEs to be shared by multiple tiles, and uses the ultra-dense and lower-power Inter-Layer Vias (ILVs) as shared buses, enabling CIM PEs to exploit the ultra-high bandwidth of M3D for inter-tile and intra-tile data transfer. Experiment result shows that the proposed M3D-enabled CIM architecture, combined with the proposed mapping method, achieves a 6.52× latency improvement, a 40.84× interconnection energy-delay product (EDP) improvement, and a 7.62× system-level EDP improvement compared to state-of-the-art CIM architecture.

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1 k-bit one-transistor-one-resistor (1T1R) array with InGaZnO x field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart.

Medical imaging is an important tool for accurate medical diagnosis, while state-of-the-art image reconstruction algorithms raise critical challenges in massive data processing for high-speed and high-quality imaging. Here, we present a memristive image reconstructor (MIR) to greatly accelerate image reconstruction with discrete Fourier transformation (DFT) by computing-in-memory (CIM) with memristor arrays. A high-accuracy quasi-analogue mapping (QAM) method and generic complex matrix transfer (CMT) scheme was proposed to improve the mapping precision and transfer efficiency, respectively. High-fidelity magnetic resonance imaging (MRI) and computed tomography (CT) image reconstructions were demonstrated, achieving software-equivalent qualities and DICE scores after segmentation with nnU-Net algorithm. Remarkably, our MIR exhibited 153× and 79× improvements in energy efficiency and normalized image reconstruction speed, respectively, compared to graphics processing unit (GPU). This work demonstrates MIR as a promising high-fidelity image reconstruction platform for future medical diagnosis, and also largely extends the application of memristor-based CIM beyond artificial neural networks.

Learning is highly important for edge intelligence devices to adapt to different application scenes and owners. Current technologies for training neural networks require moving massive amounts of data between computing and memory units, which hinders the implementation of learning on edge devices. We developed a fully integrated memristor chip with the improvement learning ability and low energy cost. The schemes in the STELLAR architecture, including its learning algorithm, hardware realization, and parallel conductance tuning scheme, are general approaches that facilitate on-chip learning by using a memristor crossbar array, regardless of the type of memristor device. Tasks executed in this study included motion control, image classification, and speech recognition.

Here we present a hybrid computing-in-memory (CIM) architecture, named M3D-CCP, by monolithically 3D integration of Si CMOS logic layer, RRAM-based CIM layer and processing-near-memory (PNM) layer with CNT/IGZO-based complementary field-effect transistor (CFET). The Si-CMOS layer was fabricated using a standard 130 nm process and served as control logic. The CIM layer consisted of ITIR arrays with analog resistive random-access memory (RRAM) for matrix-vector multiplication (MVM) operations in neural networks. The CFET-based PNM layer was fabricated with carbon nanotube FET (CNT-FET) and InGaZn$\text{O}_{\text{x}}$ FET (IGZO-FET) for caching and processing data between layers of neural networks. Both the CIM and PNM layers were fabricated using a low-temperature ($\leq$300 °c) backend-of-the-line (BEOL) process. The structural integrity and proper function of each layer were verified. Furthermore, an image super-resolution task was implemented using the fabricated M3D-CCP chip, achieving GPU-equivalent performance on the DVI2K dataset with $149\times$ lower energy consumption. Our work demonstrates the feasibility and great potential of such hybrid CIM architecture for data-abundant applications such as artificial intelligence (AI) and high-performance computing (HPC).