A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as a linear time-varying (LTV) process, as opposed to a previously published method, which models jitter generation as a linear time-invariant (LTI) process. Predictions obtained using the LTV method match jitter values obtained through exhaustive simulation with an error of up to 7.7 %, whereas errors of the jitter predicted by the LTI method exceed 57 %.

A high-voltage (HV) SOI CMOS VLSI chip has been demonstrated to transport droplets on programmable paths across its coated surface. This HV exciter for a fluidic labon-a-chip system creates dielectrophoretic forces that move and help inject droplets. Electrode excitation voltage and frequency are variable: at 100V, f(ELECmax) = 200Hz. Data communication rate is variable up to 250kHz. This 10,377 mu m-by-8210 mu m demonstration chip has a 32x32 array of nominally 100V electrode drivers dissipating 1.87W max.

Droplet-based programmable processors promise to offer solutions to a wide range of applications in which chemical and biological analysis and/or small-scale synthesis are required, suggesting they will become the microfluidic equivalents of microprocessors by offering off-the-shelf solutions for almost any fluid based analysis or small scale synthesis problem. A general purpose droplet processor should be able to manipulate droplets of different compositions ( including those that are electrically conductive or insulating and those of polar or non-polar nature), to control reagent titrations accurately, and to remain free of contamination and carry over on its reaction surfaces. In this article we discuss the application of dielectrophoresis to droplet based processors and demonstrate that it can provide the means for accurately titrating, moving and mixing polar or non-polar droplets whether they are electrically conductive or not. DEP does not require contact with control surfaces and several strategies for minimizing surface contact are presented. As an example of a DEP actuated general purpose droplet processor, we show an embodiment based on a scaleable CMOS architecture that uses DEP manipulation on a 32 X 32 electrode array having built-in control and switching circuitry. Lastly, we demonstrate the concept of a general-purpose programming environment that facilitates droplet software development for any type of droplet processor.

This paper presents a new low-power comparator circuit for use in voltage-mode CMOS multiple-valued logic (MVL) circuits. Existing MVL comparator circuits require either DC power and/or clocking power. The circuit presented in this paper uses static logic and requires no static power. It has been simulated with HSPICE using the transistor model parameter values of the TSMC T14A_2P4M 0.35-mum n-well CMOS technology. With a 3.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.38 nW total average static power and has a worst-case average critical path propagation delay of 6.4 ns. This proposed new circuit has worst case delay and layout area comparable to previously presented static quaternary logic voltage comparator circuits designed with the same technology and power supply, and power dissipation about 5 orders of magnitude less than those circuits. Also presented are simulations using the 0.35 mum technology model parameter values with an optional thick oxide and a power supply of 5 V, and simulations using the model parameter values of a 1.2-mum n-well CMOS technology and a 5 V power supply. Power, area, and speed for comparators designed in these technologies are discussed.

A computer-aided design (CAD) tool is being developed to assist in analog and mixed-signal electronic system design through the use of design optimization. This CAD tool uses technology- and implementation-independent high-level behavioral models. These computationally efficient behavioral models are expressions of the relationships among terminal variables of common electronic, MEMS, photonic, electro-mechanical, and other signal processing functions. These behavioral models include limiting behaviors in the DC, time domain, and frequency domain. These models are not based upon specific semiconductor devices, circuit configurations, or fabrication technologies. Simulations using these computationally efficient behavioral models allow designers of mixed-signal systems to evaluate alternative architectures in less time, at lower computational cost than possible with traditional semiconductor device-level simulation. With an efficient means of evaluating the performance of a mixed-signal system architecture available, we use design optimization to adjust the figures of merit of the behavioral models to achieve the desired terminal characteristics of the overall system architecture.

A new voltage-mode comparator circuit for use in CMOS multiple-valued logic circuits is introduced. Existing comparator circuits for this application use static current or clocking and thus consume static power or clocking power. In order to reduce these power requirements, we have examined static circuit designs that eliminate DC current paths when the inputs and outputs are at logical values. Elimination of DC current paths requires increased circuit complexity, layout area, and signal delay. This paper proposes comparator circuits that use static logic circuits and thus require no static current and no static (DC) power. HSPICE simulations of these circuits using model parameter values for a 0.35-/spl mu/m n-well CMOS technology and a 3.3-volt power supply show that each of these comparator circuits consumes static power on the order of nW. Simulations with the model parameter values for the thick-oxide (5-volt) option of the 0.35-/spl mu/m technology and for a 1.2-/spl mu/m (5-volt) CMOS technology are also presented. These power levels are consistent with those of standard binary CMOS logic circuits in the same technologies.

A new analog subsystem maintenance strategy is presented that can be used to improve the accuracy, reliability, yield, and testability of analog and mixed-signal ICs. This scheme is a generally applicable design approach that combines hybrid redundancy, direct subcircuit parameter adjustment (calibration), and on-chip analog function verification (built-in self-test). Improvements are realized in a system-transparent fashion through careful function block commutation. The cost is a moderate die area increase. This design strategy is applicable to a wide range of moderately complex analog functions. An example analog function is used here to illustrate this new maintenance approach. Experimental data demonstrate the capabilities of this new approach to analog IC design fortestability.

A new voltage-mode quaternary CMOS static latch circuit is presented. Only devices available in a standard digital CMOS fabrication technology-enhancement-mode NMOS and PMOS transistors with single threshold voltage values-are used. No depletion-mode devices or special transistor threshold voltages are required. Three reference voltages and ground are used to define the logic levels. The operation of the quaternary latch is experimentally verified. Using data for a standard 2-micron digital CMOS fabrication technology, best- and worst-case on-chip setup and hold times are estimated, using simulation, to be approximately 2.8 ns and 6.8 ns, respectively.

Experimental results for new low-power, reliable start-up CMOS RC oscillators are presented. The oscillators use a modified Fabre-Normand translinear current conveyor. Measurements show reliable oscillation start-up for power supply voltages that range from 1.5 V to 5 V with current consumption from 100 nA to 1.2 mA, respectively. Oscillation frequencies up to 55 MHz have been observed in circuits fabricated in a modest 2 /spl mu/m CMOS technology.

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrated several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed.

This paper presents the design of an early condition resolution circuit. The proposed circuit works in parallel with the arithmetic unit, and calculates the Equal to (EQ), Greater-than (GT), Less-than (LT), Overflow (OV), Underflow (UF), and Carry-out (C/sub out/), conditions. The proposed logic is reconfigurable, and can calculate all the conditions (mentioned above) for one 64-bit, two 32-bit, four 16-bit, or eight 8-bit signed and unsigned operands. The reconfigurability of the logic is achieved using only four control signals. Two of the control signals (Part O, Part 1) are used to partition the logic into 64, 32, 16, or 8-bit independent condition resolvers and the Sign control signal is used to control the signed/unsigned operation. The Add-Sub control signal specifies and controls the Add/Subtract operation for the condition resolution. In order to achieve high speed with reconfigurability and minimum area, new techniques are developed for calculating the conditions before the results are available. The proposed logic is designed for VLIW or Media processors, which require a high degree of reconfigurability, and high speed operation. It can also be used in MIPS family of processors for early branch condition resolution, to avoid branch stalls. Simulations of realizations in a standard digital CMOS fabrication technology show a 30% improvement in speed and a 25% savings in area using the approaches presented here.

A new voltage-mode quaternary CMOS static latch circuit is presented that is built around a binary standard CMOS logic clocked RS latch circuit. Only devices available in a standard digital CMOS fabrication technology-enhancement-mode NMOS and PMOS transistors with single threshold voltage values-are used. No depletion-mode devices or special transistor threshold voltages are required. Its operation is experimentally verified. Typical and worst-case on-chip setup and hold times are simulated to be approximately 2.8 ns and 6.8 ns, respectively

A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 μm×221 μm in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).

A new adiabatic CMOS logic that operates from a single-phase power-clock is presented. A simple and efficient power-clock generator is integrated with the logic to generate the required AC power-clock supply waveform. Circuit performance is evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings comparable to other adiabatic logic families that require multiphase power-clocks.

A new analog subsystem design approach is presented that can be used to improve the accuracy, reliability, yield, and testability of analog and mixed-signal CMOS ICs. The proposed scheme is a generally applicable design approach that combines hybrid redundancy, direct subcircuit parameter adjustment, and on-chip analog function verification. Improvements are realized in a system-transparent fashion through function block commutation. The cost is a moderate die area increase. Although applicable to any moderately complex analog function, the example analog function used to illustrate this new design approach presented here is the op amp. Experimental data demonstrate the capabilities of this new design approach.

A simple new continuous-time CMOS comparator circuit with supply-to-supply input common-mode range is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit requires an area of 416 /spl mu/m/spl times/221 /spl mu/m in a MOSIS 2-micron CMOS technology. It operates at 3 V and requires between 0.5 and 1.3 mA. Delays of between 54 and 282 ns have been measured.

Multiple-valued logic has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. Low-energy (adiabatic) logic circuits have also been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional DC power supply, these adiabatic logic circuits use 'AC' power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper we describe the adiabatic operation of a quaternary logic circuit.

Multiple valued logic (MVL) has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. These performance improvements are achieved by designers who identify signal processing functions that can benefit from the design tradeoffs possible with MVL. Since advocates of MVL are accustomed to incorporating the possible tradeoffs of MVL techniques into specific VLSI design applications, these MVL designers may be able to take advantage of new energy saving circuit design techniques that may have tradeoffs that complement those of MVL. Low-energy (adiabatic) logic circuits have been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional dc power supply, these logic circuits use “ac” power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. It is possible to integrate all power switches and control circuitry on the chip with the low-energy logic. This results in better system efficiency and simpler power distribution. In this paper, concepts of adiabatic circuit design and the use of a high-frequency resonant power clock generator for adiabatic circuits will be summarized and then their possible application to low-energy, adiabatic multiple valued logic is discussed

Automatic passband centring of an integrated high-frequency continuous-time filter has been accomplished using peak detection. In the paper an analysis of each block of the novel tuning circuit is given and the performance is evaluated in the presence of random device mismatches. Experimental results are given for an automatically tuned sixth-order bandpass filter. The filter's centre frequency deviates from its target value by less than 2%, which agrees well with theoretical calculations. Experimental prototype results further indicate that the tuning circuit is insensitive to changes in reference-frequency amplitude, and it functions well when subjected to a wide range of DC offset at its input.

Voltage-mode CMOS multiple valued logic memory circuits have been realized in a standard 2-micron p-well polysilicon-gate CMOS technology. These circuits requantize multiple-valued logical voltages during a SETUP clock mode and latch the input value during the HOLD clock mode. Using a 5 volt supply and logical voltage increments of 1.67 volts, two similar quaternary memory circuits have worst-case total SETUP and HOLD times of about 5.7 ns and 7 ns; and best single-level transition total SETUP and HOLD times of about 0.9 ns and 1 ns.