Analo and mixed-signal (AMS) integrated circuit design is often a time-consuming and costly process, due in part to manual design flows and long layout iterations. A number of tools have been developed aiming to automate the process of creating AMS designs. However, existing tools are often difficult to use due to unclear application programming interfaces (APIs), limited levels of abstraction, or insufficient control over generated collateral. We introduce Substrate, an open-source, statically typed framework for creating highly configurable schematic and layout generators using the Rust programming language. Substrate provides multiple levels of abstraction, allowing designers to navigate the tradeoff between fine-grained control over a design and increased automation. We also describe algorithms for programmatically creating and modifying circuit layouts, including two methods for automatically adjusting the aspect ratio of a layout. We use Substrate to design generators for a StrongARM comparator and a programmable resistor bank in Skywater 130nm and Intel 16nm, demonstrating 90 degree rotation, array folding, and the ability to change the aspect ratio by a factor of over 10 in both processes. These generators highlight Substrate’s ability to facilitate design reuse, process portability, and performance and area optimization.

Agentic artificial intelligence has shown great promise in automating algorithm design, but scaling similar techniques to computer microarchitecture discovery remains challenging due to vast search spaces, strict hardware budgets, and long simulation times. In this work, we present ArchAgent v2, a framework which scales automated microarchitecture search to multi-level data prefetching. While the original ArchAgent successfully discovered single-level cache replacement policies in competition settings, it does not scale to multi-level prefetching where the design space and degrees of freedom are larger. To overcome this, we introduce two new additions to ArchAgent: a cascaded evolutionary search that subdivides the design space by sequentially evolving and freezing prefetchers at individual cache levels, and a hardware-realizability feedback loop that embeds real-time size-estimation directly into the evolution process. Evaluated under identical rules of the 4th Data Prefetching Championship (DPC4), ArchAgent v2 automatically designs a three-level prefetcher that outperforms the winning hand-designed solution, further demonstrating automated agentic discovery as a useful tool for computer architects. Our discovered policy achieves a 3.8\% geometric mean IPC speedup over the baseline overall and a 0.3\% improvement over the prior champion, BertiGO. On low-bandwidth single-core configurations, our policy yields a 4.6\% performance speedup compared to only 2.6\% for BertiGO. However, multi-core evolution still remains a significant challenge due to simulation latency impeding evolution speed. Finally, our profiling of an ArchAgent evolution of over 12,000 candidate designs provides key insights into how automated evolutionary agents explore and synthesize complex microarchitectural logic.

Three-dimensional reconstruction in robotics combines heterogeneous workloads: INT8 DNNs for depth estimation (DE) and feature extraction (FE), and FP32 sparse linear algebra (LA) workloads for simultaneous localization and mapping (SLAM). These tasks stress heterogeneous computing, accelerator integration, and scheduling. We present MAVERIC, a 16-mm(2) system-on-chip (SoC) in Intel 16 with 4 CPU cores and 13 accelerators (eight INT8, five FP32) that executes diverse workloads, including the full DE and SLAM pipeline end-to-end, including loop closure (LC). A hierarchical, generator-driven SoC flow and a multi-layer 2-D-mesh network-on-chip (NoC) streamline integration of on-chip components and scale the design. A lightweight remote CPU-accelerator interface with a custom hardware protocol enables efficient scheduling and parallel utilization of heterogeneous accelerators. We compress the vocabulary tree (VT) for on-chip LC and map numerical optimization tasks to FP32 accelerators, providing full on-chip SLAM support. MAVERIC operates at up to 1 GHz, achieves 8 TOPS/W peak efficiency, and processes 72 FPS 10 mJ/frame for end-to-end DE and SLAM. These results demonstrate that mixed-precision, many-accelerator SoCs are an effective architecture for real-time, energy-efficient robotics perception.

Sirius is a dual-chiplet system targeting multimodal embodied AI on resource-constrained platforms. It integrates heterogeneous RISC-V Vector (RVV) cores with dense and sparse accelerators to efficiently execute diverse workloads, including transformers, vision backbones, and robotics pipelines. Sirius addresses deployment challenges through three innovations: (1) support for diverse non-uniform quantization schemes via programmable LUTs and outlieraware dense and sparse (D+S) decomposition, (2) a logically shared, physically distributed scratchpad memory system enabling kernel fusion and heterogeneous streaming, and (3) chiplet-based disaggregation using a custom interconnect. Fabricated in Intel16, Sirius delivers up to 2.24 TFLOPS/W for dense GeMM, 7.11 TFLOPS/W for SpMV, and achieves end-to-end 16 tokens/sec at 23 mJ/token on Qwen2.5-0.5B SLM, and 0.97 TFLOPS/W for robotics perception.

Mixture-of-experts (MoE) architectures have turned LLM serving into a cluster-scale workload in which communication consumes a considerable portion of LLM serving runtime. This has prompted industry to invest heavily in expensive high-bandwidth scale-up networks. We question whether such costly infrastructure is strictly necessary. We present the first systematic cross-layer analysis of network cost-effectiveness for MoE LLM serving, comparing four representative XPU (e.g., GPU/TPU) topologies (scale-up, scale-out, 3D torus, and 3D full-mesh). We find that lower-cost switchless topologies are more cost-effective than the scale-up topology across all serving scenarios explored, improving cost-effectiveness by 20.6-56.2

We present an agile methodology based on the open source Chipyard framework used for designing and validating manufacturable and performant heterogeneous RISC-V SoCs within the constraints of 15-week semesters by classes composed primarily of undergraduate students. Chipyard integrates configurable, generator-based IP blocks and flows, including the modular VLSI flow, Hammer, developed over a decade of tapeouts in different technologies. Students iterate their custom RTL and AMS blocks through integration, verification, and place-and-route, then write full-stack applications, characterizing performance. One recent semester’s class chips in FinFET are described: COSMIC (FFT, convolution, DMA accelerators), MELLIS (sparse‑matrix, convolution, quantized transformer engines, near‑memory MAC), and SCμM‑V (low-power crystal-free transceiver, general-purpose AFE, on-chip power management, clock generation). For example, COSMIC reaches 1.25 GHz, accelerates compute 2-12× with energy savings, and runs live demos. New documentation and infrastructure, such as the new bring-up platform, Baremetal, make Chipyard even more accessible.

Agentic artificial intelligence shows great promise for radically improving the pace of innovation in hardware/software co-design research across computer architecture, systems, compilers, and VLSI. Thus far, however, applications of AI in these contexts have generally been demonstrated in isolated settings on small-scale problems, due to the difficulty of designing and deploying complex AI-infused hardware and software development workflows. This paper introduces CHIA, an open-source hardware/software co-design framework for agile and principled research on the application of AI to co-design. CHIA treats the productive construction and scalable deployment of the co-design flow itself as a first-class objective. In CHIA, agentic AI-driven hardware and software design flows are expressed as CHIA loops: directed cyclic graphs whose nodes execute various system-on-chip design tools, microarchitectural simulators, software build systems, AI models, evolutionary coding agents, and more. The CHIA library provides node implementations for many popular tools, including Chipyard, gem5, ChampSim, FireSim, Hammer (thus several commercial ASIC CAD tools), Vivado, AlphaEvolve, AdaEvolve, and many others. CHIA also provides a broad set of features to conduct principled science around these flows. These include isolation between AI models and hardware tools, profiling mechanisms, fault-tolerant execution, and reliability at scale across hundreds of heterogeneous systems (CPUs, FPGAs, GPUs, etc., across public cloud/on-prem.). To showcase CHIA, we present five CHIA loops as case studies: (1) automatic RTL-to-gem5 simulator alignment, (2) LLM-driven implementation of microarchitectural features in RTL, (3) agentic, IPC-aware critical path optimization, (4) evolutionary architectural discovery, and (5) maintainer-friendly agentic GitHub issue fixing.

We introduce Cygnus, an energy-efficient octa-core RISC-V vector processor, compliant with the RISC-V vector extension (RVV) 1.0 specification, specifically designed for digital signal processing (DSP) and robotics applications. This system-on-chip (SoC) features dynamic instruction scheduling with short-vector lengths at the vector core level and employs a big/little architecture with tightly coupled memory (TCM) at the SoC level. The TCM design enables efficient data streaming across the cores, bypassing the cache hierarchy for streaming applications. Cygnus achieves a high average utilization of 90% across general matrix multiply (GEMM) and convolution (CONV) kernels, demonstrating energy efficiencies of 414 GOPS/W for INT8 GEMM and 109 GFLOPS/W for FP32 GEMM. In a typical computer vision kernel that implements denoising using a non-local means (NLMs) algorithm, the SoC provides a latency of 3.7 ms with an energy consumption of 518 mu J per frame. Moreover, we demonstrate the adaptability of our approach using our SoC in a drone control application that employs a model-predictive control (MPC) algorithm based on TinyMPC. Cygnus, running the Zephyr real-time operating system (RTOS), manages control for three drones while optimizing performance through vectorization, achieving over 3.5 & times; improvement in solve time and significant reductions in position-tracking error at higher clock frequencies. The implementation demonstrates enhanced the real-time performance and accuracy compared with baseline scalar methods.

Agile hardware design flows are a critically needed force multiplier to meet the exploding demand for compute. Recently, agentic generative AI systems have demonstrated significant advances in algorithm design, improving code efficiency, and enabling discovery across scientific domains. Bridging these worlds, we present ArchAgent, an automated computer architecture discovery system built on AlphaEvolve. We show ArchAgent's ability to automatically design/implement state-of-the-art (SoTA) cache replacement policies (architecting new mechanisms/logic, not only changing parameters), broadly within the confines of an established cache replacement policy design competition. In two days without human intervention, ArchAgent generated a policy achieving a 5.3 Agentic flows also enable "post-silicon hyperspecialization" where agents tune runtime-configurable parameters exposed in hardware policies to further align the policies with a specific workload (mix). Exploiting this, we demonstrate a 2.4 Finally, we outline broader implications for computer architecture research in the era of agentic AI. For example, we demonstrate the phenomenon of "simulator escapes", where the agentic AI flow discovered and exploited a loophole in a popular microarchitectural simulator - a consequence of the fact that these research tools were designed for a (now past) world where they were exclusively operated by humans acting in good-faith.

This work addresses the use of reinforcement learning in the design of analog and mixed-signal (AMS) circuits. With recent advanced angstrom-technology-nodes adding new complexities, this highly manual process has grown increasingly challenging and less aligned with conventional design intuition. The presented approach modifies circuit topologies at the transistor-level to meet design requirements. We present, for the first time, a deep reinforcement learning (RL) framework capable of generating novel circuit topologies by using graph encodings for targeted specifications, starting from a minimal expert design and a user-specified testbench. To highlight the capabilities of the approach, we demonstrate the topological modification and expansion of incomplete sub-circuits to satisfy user-provided performance for three different types of circuits: 1) a ring oscillator, 2) a comparator, and 3) an operational transconductance amplifier. Our results demonstrate that our method is capable of generating previously unseen topologies that reach user-defined performance targets. In each design case, 100% of generated circuit netlists are correct by construction and over 90% of generated circuits demonstrate intended functionality and targeted performance when simulated with commercial tools.

We analyze OCS-based networks for LLM inference, showing sub-700 ns reconfiguration is critical to outperform EPS without high link fan-out. High link fan-out can provide competitive performance even with slower reconfiguration across collective communication patterns.

Analog and mixed-signal circuit design automation has remained a longstanding objective spanning several decades of research. This article examines how machine learning (ML) can help realize new capabilities in this domain. AstRL [analog and mixed-signal (AMS) synthesis with reinforcement learning], a topology-level circuit design framework, is introduced to demonstrate recent progress in deep learning-based approaches toward automation. We then position AstRL within a broader survey of ML approaches for circuit design. From these examples, we distill several key development principles, including the importance of formulating ML methods that reflect realistic design challenges, leveraging simulation-guided training, and integrating expert knowledge. These core ideas further highlight a principled path toward applying modern ML architectures that are based on practical design considerations.

Analog and mixed-signal (AMS) integrated circuits (ICs) lie at the core of modern computing and communications systems. However, despite the continued rise in design complexity, advances in AMS automation remain limited. This reflects the central challenge in developing a generalized optimization method applicable across diverse circuit design spaces, many of which are distinct, constrained, and non-differentiable. To address this, our work casts circuit design as a graph generation problem and introduces a novel method of AMS synthesis driven by deep reinforcement learning (AstRL). Based on a policy-gradient approach, AstRL generates circuits directly optimized for user-specified targets within a simulator-embedded environment that provides ground-truth feedback during training. Through behavioral-cloning and discriminator-based similarity rewards, our method demonstrates, for the first time, an expert-aligned paradigm for generalized circuit generation validated in simulation. Importantly, the proposed approach operates at the level of individual transistors, enabling highly expressive, fine-grained topology generation. Strong inductive biases encoded in the action space and environment further drive structurally consistent and valid generation. Experimental results for three realistic design tasks illustrate substantial improvements in conventional design metrics over state-of-the-art baselines, with 100

This work presents a $4\times 4$ fully passive charge-domain configurable beamformer integrated into 9-bit SAR ADCs in Intel 16 process, which operates up to 500MHz, achieving over 33dB spatial notch with 52.1mW per RX element. 1-degree resolution, energy-efficient switched-capacitor phase shifters with on-chip calibration ability are implemented using existing circuits in SAR ADC, realizing beamforming with only 15% area and 5% power overhead.

MAVERIC is a 4 core, 13 INT8/FP32 accelerator unit (AU) 16mm2 SoC in Intel 16, for ML and robotics applications. 3D reconstruction (3DRecon) robotics application combines depth estimation (DE) and simultaneous localization and mapping (SLAM) for perception tasks, posing compute demand, accelerator integration, and scheduling challenges. MAVERIC operates at up to 1 GHz and achieves 8 TOPS/W peak energy efficiency (Eeff). It supports loop closure (LC) and delivers 10 mJ/frame and 72 FPS at the end-to-end DE and SLAM.

Simultaneous Localization and Mapping (SLAM) plays a crucial role in robotics, autonomous systems, and augmented and virtual reality (AR/VR) applications by enabling devices to understand and map unknown environments. However, deploying SLAM in AR/VR applications poses significant challenges, including the demand for high accuracy, real-time processing, and efficient resource utilization, especially on compact and lightweight devices. To address these challenges, we propose SuperNoVA, which enables high-accuracy, real-time, large-scale SLAM in resource-constrained settings through a full-stack system, spanning from algorithm to hardware. In particular, SuperNoVA dynamically constructs a subgraph to meet the latency target while preserving accuracy, virtualizes hardware resources for efficient graph processing, and implements a novel hardware architecture to accelerate the SLAM backend efficiently. Evaluation results demonstrate that, for a large-scale AR dataset, SuperNoVA reduces full SLAM backend computation latency by 89.5% compared to the baseline out-of-order CPU and 78.6% compared to the baseline embedded GPU, and reduces the maximum pose error by 89% over existing SLAM solutions, while always meeting the latency target.

This paper introduces NeCTAr (Near-Cache Transformer Accelerator), a 16nm heterogeneous multicore RISC-V SoC for sparse and dense machine learning kernels with both near-core and near-memory accelerators. A prototype chip runs at 400MHz at 0.85V and performs matrix-vector multiplications with 109 GOPs/W. The effectiveness of the design is demonstrated by running inference on a sparse language model, ReLU-Llama.

We introduce Cygnus, an energy-efficient octa-core RISC-V vector processor compliant with the RVV 1.0 specification targeting digital signal processing (DSP) applications. This chiplet features dynamic instruction scheduling with short vector lengths at the vector core level and a big/little architecture with tightly-coupled memory at the SoC level, facilitating efficient streaming data flow across cores. Cygnus demonstrates a high average utilization of 90% across GEMM and CONV kernels, achieving leading energy efficiencies of 414 GOPS/W for INT8 GEMM and 109 GFLOPS/W for FP32 GEMM. In a representative computer vision kernel implementing denoising using a non-local means algorithm, the chiplet delivers a latency of 3.7 ms with an energy consumption of 518 μJ/ frame.

The growing demand for intelligent audio and speech signal processing on mobile terminals requires energy efficient programmable support for digital signal processing (DSP) and machine learning (ML) applications. This paper presents COSMIC, a heterogeneous RISC-V SoC designed for DSP/ML workloads. Leveraging an agile open-source design flow, the $2 \text{mm} \times 2 \text{mm}$ SoC, fabricated in Intel 16 FinFET, integrates four RISC-V vector cores, a single-path delay feedback FFT accelerator, convolution accelerator, and programmable direct memory access engine running at up to 1.25 GHz, enabling efficient execution of spectral analysis, filtering, and machine learning workloads. This work accelerates convolution compute by up to $\mathbf{1 2 x}$ and FFT transforms by $\mathbf{2 x}$. The fully featured SoC runs a 260 k parameter Llama model at up to 85 tok $/ \text{sec}$ and 1.11 $\text{mJ} /$ tok and real-time audio beamforming applications.

We present BAG $3{++}$ , an extensible analog/mixed-signal (AMS) design framework for layout-aware design. BAG $3{++}$ realizes a unified design environment that merges schematic, layout, and verification views into a single development interface. We further introduce new automated design features that enable rapid automation and optimization across a range of performance specifications, processes, and applications. We demonstrate the practical use of these features through (a) a bit-reconfigurable successive-approximation-register (SAR) analog-to-digital converter (ADC) implemented in the open-source Skywater 130nm process and (b) an ultra-high speed output driver optimized in two modern processes. BAG $3{++}$ interfaces with both commercial and open-source design frameworks, and the extensibility of BAG $3{++}$ is further illustrated through the integration of an open-source simulator.