In 0.17 Al 0.83 N/GaN high‐electron‐mobility transistor (HEMT) using GaN‐on‐Insulator (GaNOI) technology via 200 mm wafer bonding technique is developed with good DC and RF performance and high f T /f max . Measurements obtained from X‐Ray diffraction and micro‐Raman spectroscopy have demonstrated a 5% reduction in “a lattice strain,” which results in the improvement of the sheet resistance ( R sh ) from 301 to 284 Ω □ −1 . A 120 nm gate‐length device achieves a peak f T up to 96 GHz which yields a f T × L g value of 11.5 GHz μm, which compares favorably with reported GaN‐based HEMTs on Si. These results demonstrate that GaNOI HEMT on Si is an attractive candidate for future mm‐wave applications. The implementation of GaNOI technology facilitates the integration of GaN devices into a chip alongside complementary metal–oxide–semiconductor technology that opens up the potential for integrated high‐power and RF applications, enabling more compact and efficient systems.

We report a first demonstration of GaAs HBT-OI fabricated using epitaxy growth, wafer bonding and layer transfer technique. Excellent bonding yield was found on the 200 mm GaAs HBT-OI wafer with wafer bowing of less than 90 & mu;m. A dc gain of 20, and cutoff frequency (fT) of 6.5 GHz was measured for a device with emitter finger of 6 x 18 & mu;m2. Its ideality factors for collector and base were 1.19 and 1.44, respectively. These results showed that the method of GaAs HBT-OI fabrication can be used for future integration of III-V on a common Si platform with low RF power dielectric attenuation.

Designing the next generation of high-resolution displays requires high pixel density per area and small pixel sizes without compromising the optical quality. Quantum dots (QDs) have been demonstrated as a promising material system for down-conversion of blue emission as they provide pure colors on the wide color gamut. However, for high color-conversion efficiency, the required QD film thickness has not been compatible with small pixel sizes. In this work, we develop a new type of freestanding QD-based color converter for efficient optical down-conversion from inorganic blue light-emitting diodes (LEDs) in a color-by-blue configuration. CdSe/ZnS core-shell QDs in a UV-curable polymer matrix are encapsulated within cavities formed by patterning and bonding a pair of patterned quartz substrates. By controlling the required QD thickness and the pixel size independently, we demonstrate freestanding monochrome red and green converters with small pixel sizes down to 5 × 5 μm2 and a high resolution of >3600 ppi. The optical studies show that the QD film thickness required for efficient color conversion can be successfully realized even for the small pixel sizes. We further combine green and red pixels in a single converter to achieve white emission when combined with blue LED emission. The QD color converter design and processing are decoupled from the LED fabrication and can be easily scaled to wafer-size integration with arbitrary pixel sizes for QD-based RGB displays with ultrahigh resolution.

We report an In0.3Ga0.7As HBT device grown on a 200 mm Si wafer using GeSi as virtual starting substrate and InAlAs as the compositionally graded buffer layer from GaAs to In0.3Ga0.7As lattice constant. A DC gain, emitter base, and base-collector ideality factors of 10, 1.43, and 1.56, respectively, are obtained for a device with an emitter area of 40 x 50 mu m(2). Small-signal simulation of an In0.3Ga0.7As HBT device with 2 x 8 mu m2 emitter area shows that current gain cutoff frequency (fT) and maximum cut-off frequency (fMax), of 50 GHz and 220 GHz, respectively, can be achieved with base doping and layer thickness of 2 x 10(18)cm(-3) and 30 nm, respectively.

AlN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) on silicon substrate using in situ SiN as gate dielectric were fabricated and their RF power performance at mobile system-on-chip (SoC) compatible voltages was measured. At a mobile SoC-compatible supply voltage of V d = 3.5 V/5 V, the 90 nm gate-length AlN/GaN MISHEMTs showed a maximum power-added efficiency of 62%/58%, a maximum output power density (P outmax) of 0.44 W mm−1/0.84 W mm−1 and a linear gain of 20 dB/19 dB at the frequency of 5 GHz. These results suggest that the in situ-SiN/AlN/GaN-on-Si MISHEMTs are promising for RF power amplifiers in 5G mobile SoC applications.

The performance of a pentacene organic thin film transistor (OTFT) is discussed here where the substrate consists of a self-assembled monolayer (SAM) formed from octadecyltrichlorosilane (OTS) on the gate insulator. By changing the substrate from hydrophilic to hydrophobic interface defects are minimized. OTS SAM was studied for two samples according to OTS density 0.5 wt % and 1.0 wt % based on chloroform solution. The water contact angle was measured to investigate OTS growth and distribution. AFM and SEM were used to give organic thin film topography and morphology. The OTFT with 0.5 wt % OTS has a higher mobility and on/off ratio than the OTFT with 1.0 wt % OTS but has an increased threshold voltage. At the same time, the hysteresis at room temperature almost disappeared due to the OTS SAM processing.

There is great interest in increasing the use of magnesium (Mg) alloys in transportation applications to reduce weight. The use of these alloys would increase if their strength and castability were improved. Through grain refinement, it is possible to achieve significant improvement in specific mechanical properties such as strength and hardness. For aluminum (A1)-containing Mg alloys, a commonly used grain refiner is hexachloroethane (C₂Cl₆). Though effective, C₂Cl₆ use releases harmful chlorinated hydrocarbons. It is therefore desired to find novel grain refiners that are effective and environmentally safe. This thesis focused on the grain refinement of AZ9lE alloy with three refiners: Al-5TiB₂, Al-A1₄C₃ and ZnO. The refiners were chosen due to their known grain refinement efficiency in low-Al Mg or Mg-Zn alloys. Castings with each refiner were made in graphite molds to establish i) the optimum addition levels to achieve the smallest average grain size and ii) the effect of holding time on fading of grain refinement efficiency. These castings ere used to collect thermal data and sectioned for microscopy and hardness testing. Castings were also made with the optimum parameters in a permanent mold specifically designed to investigate hot tearing susceptibility. The results indicated that all three additions enabled grain refinement of the base alloy, and no fading of grain refiner efficiency was observed. These refiners transformed the coarse dendritic microstructure in AZ9lE to one that was equiaxed and globular. At optimal levels, the refinement mechanism was heterogeneous nucleation. Also, hot tearing was significantly decreased with all refiners except for ZnO. The excess Zn from ZnO addition led to an increase in the freezing range, thus increasing the hot tear severity. The hardness of AZ9lE did not increase with ZnO addition as it did with the other two refiners.

In this article, we demonstrate the Ti/TiN/Al (15/50/50 nm) ohmic contact on InGaP/GaAs heterojunction bipolar transistors (HBTs) epitaxially grown on 200-mm Si substrate. We study the rapid thermal annealing (RTA) effect of the metal stack on both n-type InGaAs and p-type GaAs. The dc characteristics of the HBT devices fabricated using the Ti/TiN/Al metal contacts have been analyzed. Contact resistances ${(}{R}_{c}{)} < 0.1~\Omega \cdot $ mm for n-InGaAs and $0.8~\Omega \cdot $ mm for p-GaAs can be achieved. A dc current gain of 45 with a collector–base breakdown voltage (BV cbo ) of 15.65 V is achieved. The ideality factor of the emitter–base current ( ${n}_{b}$ ) and base–collector current ( ${n}_{c}$ ) is 1.03 and 1.44, respectively, after RTA at 450 °C. The dc characteristics remain stable upon prolonged annealing at 450 °C for 45 min. This high thermal budget non-gold ohmic contact is suitable for Si-CMOS integration and enables the potential for hybrid III-V CMOS technology for 5G and mm-wave applications.

100 nm T-gate GaN-on-Si HEMTs fabricated using CMOS-compatible Au-free Ta/Al ohmic and Ti/Al gate contacts are reported in this work. The device exhibited a maximum drain current of 1.82 A/mm, a peak transconductance of 489 mS/mm, a cut-off frequency f(T) of 102 GHz, and a maximum oscillation frequency f(max) of 114 GHz. Good RF performance comparable to their counterparts with Au-contained processes is achieved, demonstrating its potential for cost-effective microwave and mm-wave applications.

The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control circuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-, double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Meanwhile, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.

Noninvasive in vivo measurements of glycemia in 8 living non anesthetized mice were done using a microwave spiral sensor (MSS). The D-glucose concentration in the blood of the animals was measured in the 80–350 mg/dL concentration range using microwaves of frequencies from 4–5 GHz. Aqueous D-glucose solution with concentrations from 0 to 6% was orally injected into the mice and the change in the total glycemia was monitored in real time. In particular, two sets of measurements were done. In the lower frequency regime, using a resonance of about 4.1 GHz, for a 6% blood glucose concentration, there was a frequency shift of 48 MHz and a reflection coefficient S11 change of 15 dB, while in the higher frequency regime, about 5 GHz, the frequency shift was 59 MHz with a S11 change of 1.6 dB. These in vivo results show a signal-to-noise ratio (SNR) of 24 dB and a minimum detectable glucose level was determined to be 10 mg/dL. This is in contrast with in vitro measurements, using the same spiral sensor, which show 32 dB SNR and a minimum detectable glucose level of 5 mg/dL. The results show the utility and sensitivity of the MSS for noninvasive biological investigations of glycemia in living animals.

In this work we demonstrated InAlN/GaN High Electron Mobility Transistors (HEMTs) on silicon substrate fabricated with Si CMOS-compatible metallization process for RF power amplifier applications in 5G low power mobile SOCs. The HEMTs exhibited a maximum drain current ( $I_{\text{dmax}}$ ) of 1.9 A/mm, a peak transconductance ( $g_{\mathrm{m}}$ ) of 490 mS/mm, a cutoff frequency ( $f_{\mathrm{T}}$ ) of 215 GHz and a maximum oscillation frequency ( $f_{\max}$ ) of 97 GHz. An effective electron velocity of $1.49\times 10^{7}$ cm/s was extracted through delay time analysis. At a mobile SoC-compatible supply voltage of $V_{d}=5\ \mathrm{V}$ , the device shows a high maximum output power density ( $P_{\text{outmax}}$ ) of 1.24 W/mm, a peak power-added efficiency (PAE) of 45%, and a gain of 16 dB at 5 GHz. These results indicate the great potential of InAlN/GaN HEMTs on silicon for high performance and low-cost RF power amplifiers in 5G mobile SoC applications.

GaN-on-Si high electron mobility transistors (HEMTs) with 80 nm gate length fabricated using Si CMOS-compatible Ta/Al ohmic and Ti/Al gate contacts are reported in this work. The device with a source–drain distance (Lsd) of 750 nm exhibited a high cut-off frequency (fT) of 210 GHz. A three-terminal off-state breakdown voltage (BVds) of 46 V and a high Johnson's figure-of-merit (=fT × BVds) of 8.8 THz V have been achieved in a device with Lsd of 1.5 μm. These results show the great potential of GaN-on-Si HEMTs to realize high-performance-to-cost ratio mm-wave devices through mass production using current Si foundries.

N-p-n InGaP/GaAs double heterojunction bipolar transistor has been successfully grown on a 200 mm Ge/Si wafer using metalorganic chemical vapor deposition with low defect density of 107 cm-2. Non-gold metals of Ni/Ge/Al and Ti/Al are used to form the ohmic contact for small pieces device fabrication. Both direct-current (dc) and high-frequency characteristics of the device were measured. The device with emitter area of 6 × 8 μm2 shows a dc gain of 55 at a collector current of Ic = 4 mA, with high collector-emitter breakdown voltage of ~17 V. The high-frequency response with cutoff frequency (fT) of 23 GHz and maximum available frequency (fmax) of 10 GHz can be achieved. These results demonstrate that InGaP/GaAs double heterojunction bipolar transistor grown on low defect density Ge/Si wafer has the potential for realizing III-V CMOS integrated platform for high-frequency applications.

This paper presents a logic inverter circuit consisting of both CMOS and GaN devices to drive high-torque DC motors requiring high voltages in various robotics applications. The GaN+CMOS inverter can be monolithically integrated with CMOS digital circuits on a single die, accommodating a 5V CMOS logic level input and providing a 30V output voltage using depletion-mode GaN HEMTs without negative gate bias circuitry. Electro-thermal simulations are also performed to analyze the temperature of CMOS devices affected by nearby GaN HEMTs.

Low threading dislocation density (TDD) in GaAs epitaxial layers grown on silicon substrate (e.g. TDD < 106 cm−2) is critical for GaAs-based optoelectronic and high-performance electronic devices on silicon. Ge buffers and InxGa1-xAs/GaAs superlattice layers (SLs) are commonly used to reduce the TDD in GaAs epitaxial layers grown on Si wafers. In previous reports, TDD of ~107 cm−2 in GaAs and InGaP layers grown on 200 mm Si wafers was achieved by using Ge buffers only (e.g. Wang et al 2017 Semicond. Sci. Technol. 32 125013) and TDD of ~106 cm−2 in GaAs epi-layers for quantum dot lasers on Si was achieved by using SL insertion layers (e.g. Shang et al 2019 IEEE J. Sel. Top. Quantum Electron. 25 1502207). In this work, the effectiveness of the dislocation filtering effect of InxGa1-xAs/GaAs SLs combined with Ge buffers is investigated. The results are compared with wafers where InxGa1-xAs/GaAs SLs were directly grown on GaAs-on-Si buffers without Ge buffers. The InxGa1-xAs/GaAs dislocation filter layers (DFLs) consisted of 10 nm InxGa1-xAs/10 nm GaAs layers superlattice spaced by GaAs layer. Then, 1000 nm thick InGaP layers were grown on top of the DFLs to characterize the effect. Transmission electron microscopy, etch-pit density, x-ray diffraction, and photoluminescence were performed to characterize the quality of the materials. Our results indicate that for the growth with Ge buffers there was no significant difference in the final TDDs in the InGaP layers compared with a reference wafer that did not have DFL. For the growth without Ge buffers, the dislocation filtering effect was indeed observed, although it was not as significant as in other reports. For all wafers with DFLs, large wafer bow and dense film cracks appeared, which hinders the practical application of this method.

The needs of electronics are endless. The complexity in designing a circuit to meet high demand markets has increased daily. Furthermore, the urge for high power gain for high-efficiency RF applications leads to searching a replacement of Si material. III–V compound semiconductor (CS) materials provide a promising technology booster but integrating into the state-of-the-art Si equipment for VLSI faces some challenges for circuit designs and device fabrication. To ease the design complexity, Process Design Kit (PDK) has been widely used for modern semiconductor designs. This paper presents cross-platform III–V/Si circuit simulation, schematic and layout design, and integration of III–V/Si design verification for VLSI on 200-mm wafer in Si CMOS fabrication environment.

Integrate LEDs and CMOS circuits on large Si wafers can enable numerous new applications and add new functions to Si integrated circuits. In the past efforts on the integration of AlGaInP LEDs and CMOS circuits on 200 mm Si wafers, we have solved fundamental problems such as III-V semiconductor heteroepitaxy on Si substrates, wafer bow control, and bonding of LED wafers with CMOS wafers. Our latest achievement in this work is the demonstration of working devices processed on 200 mm LED wafers. We will present our efforts on the development of CMOS-compatible Ohmic contacts, 200 mm wafer-scale processing, and characteristics of the devices. We have evaluated different metals as CMOS-compatible low-resistance Ohmic contacts to the AlGaInP LEDs. We will compare the performance of the LEDs using the different metal contacts. We will present our progress on the process of CMOS-bonded LED wafers. Different from the LED-only wafers, the process of CMOS-bonded LED wafers can only be done in opened trenches, which adds extra difficulties. In addition, we will show the method we have developed for the re-entry of the CMOS-LED integrated wafers to the CMOS foundries for the end-of-line metal interconnections. Finally, potential applications using the CMOS-integrated LEDs will be discussed.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafer, two issues need to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and create unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with additional diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer to a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate is realized.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafers, two issues have to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and results in unbonded area. To address this, a CMP process that using conventional SiO2 slurry with the addition of diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is that the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer onto a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate can be realized.