This study investigates the impact of seed layer materials on ferroelectric La-doped (Hf, Zr)O2 (La:HZO) capacitor, designed with back-end-of-line (BEOL) compatibility. The seed layers influence the number and size distribution of HZO nano-crystallites in the as-grown state due to differences in surface passivation and oxidation potential, ultimately leading to variations in the final grain size after post-metallization annealing (PMA). An inverse relationship is observed between the initial number of nano-crystallites and the final grain size, attributed to impingement between growing grains during annealing. These distinct grain growth behaviors drive different phase evolutions in the HZO films, depending on pathways in the phase diagram. While WO3 and ZrO2 seed layers result in undesirable grain size distributions and pathways in the phase diagram leading to inferior electrical performances, the TiO2 seed layer yields intermediate nano-crystallite numbers and sizes, promoting sufficient ferroelectric orthorhombic phase formation. These findings indicate that precise control of HZO nanocrystallite formation through seed layer engineering with careful consideration of phase evolution mechanisms, is essential for continued scaling of HZO film thickness in advanced ferroelectric devices.

Area-selective deposition (ASD) shows promise for tackling nanofabrication challenges for advanced nanoelectronic devices. Understanding the proximity effects during ASD in nanopatterns is important to ensure atomic scale precision of deposition. This work reveals and analyzes proximity effects during GeTe ASD by atomic layer deposition (ALD) with the well-known dechlorosilylation chemistry and an aminosilane inhibitor. The proximity of the TiN growth and the trimethylsilyl-terminated SiO2 nongrowth area in a line-pattern with 35 nm critical dimension leads to an altered GeTe thickness profile and a higher selectivity compared to the nonpatterned SiO2 substrate. The GeTe film on the TiN growth area shows a well-controlled, inverted U-shaped profile, different than conformal deposition typical for ALD. The ASD process in a passivated trench is mimicked using a previously developed stochastic lattice growth model, and the model results indicate that the observed edge profile is consistent with electrostatic interactions between the Te precursor's Si(CH3)3 ligands on the growth surface and the trimethylsilyl-groups present on the adjacent vertical passivated SiO2 nongrowth surface. The selectivity increase is attributed to diffusion-mediated migration of adspecies from the nongrowth to the growth area. We conclude that this ASD process is influenced by the proximity of growth and nongrowth surfaces by processes that go beyond the well-known self-limiting surface reactions of ALD. This work opens opportunities to tune the thickness profiles during ALD in nanopatterns beyond conformal deposition by the substrate and deposition conditions. The insights into the mechanisms of proximity effects are relevant to enable atomic-scale precision in ASD for various materials and applications in nanofabrication, including nanoelectronic device fabrication by ALD and by other deposition techniques.

Understanding and controlling oxygen exchange at the interface of Hf x Zr1-x O2 (HZO) are critical for stabilizing ferroelectricity in ultrathin films. In this work, we demonstrate that functional capping layers serve as active oxygen reservoirs that modulate the tetragonal to orthorhombic phase transition in both solid solution (SS) and nanolaminate (NL) HZO films. X-ray photoelectron spectroscopy reveals distinct reducibility trends among the capping materials, directly correlating oxygen transfer with changes in crystallinity, grain morphology, and ferroelectric behavior. Comprehensive structural and electrical analyses using X-ray diffraction, atomic force microscopy, transmission electron microscopy, energy-dispersive spectroscopy, and polarization-electric field curve measurements show that WO3 delivers stronger oxygen injection capability and yields superior ferroelectric response in SS-HZO, whereas Nb2O5 optimizes remnant polarization in NL-HZO. Moreover, engineering the sublayer thickness in NL-HZO enables a tunable balance between improved ferroelectric behavior and enhanced reliability. These findings establish oxygen-transfer engineering via functional capping layers as a powerful design principle for achieving robust and energy-efficient ferroelectricity in sub-6 nm HZO, offering a promising pathway toward next-generation ultralow-power ferroelectric memory technologies.

Ternary GeAsSe alloys that exhibit Ovonic Threshold Switching are promising selector materials for memory arrays. This application requires conformal deposition of GeAsSe films with good composition control on high-aspect-ratio structures, preferably by Atomic Layer Deposition (ALD). However, there are currently no GeAsSe ALD processes reported in literature. Reactive precursors should, therefore, be identified-a challenging task for ternary materials due to the numerous precursor combinations. In this work, we reveal favorable and unfavorable precursor combinations by computing the precursor gas-phase reaction energies using ab initio simulations. The results are consistent with experiments, as demonstrated ALD processes show exoenergetic reactions. Favorable additional chemistries are silylation, alkylation, and hydrogen transfer, irrespective of the central element (Ge, As, and Se), which provides promising pathways to enable GeAsSe ALD. Selenium coreactants show similar reactivity with germanium and arsenic precursors, implying that demonstrated GeSe ALD precursor chemistries can also be used for As2Se3 ALD. The presented insights into precursor reactivity and ligand reactivity trends may advance the development of deposition processes for novel thin films, including GeAsSe, using ALD, chemical vapor deposition, or area-selective deposition.

Herein, the operation of a GeSe ovonic threshold switch (OTS) is studied as a self‐selecting memory cell based on the polarity effect. From the observed operating current ( I op ) dependence and area scaling behavior, the critical role of Joule heating in ensuring exceptionally large memory window in this material is confirmed. The underlying mechanism is further investigated by means of chemical analysis and is confirmed to be caused by polarity‐dependent atomic migration under high‐ I op regime, consistent with elemental segregation due to electronegativity contrast. More specifically, selective diffusion of Ge atoms through the TiN layer into negatively biased top electrode stack is observed. At the same time, there is no sign of a similar process for Se atoms under opposite voltage polarity. Based on these observations, a novel memory concept utilizing a selective diffusion barrier is proposed. Furthermore, under low‐ I op regime, no major composition change is observed, leaving room for alternative interpretation of the polarity effect under such conditions. Finally, it is demonstrated that functional GeSe OTS‐only memory is fabricated with atomic layer deposition, making it suitable for vertical 3D integration to enable low‐cost applications.

Ge2Sb2Te5 (GST) is a well-known phase change material used in nonvolatile memory devices, photonics, and nonvolatile displays. This study investigates the impact of precursor sequence during atomic layer deposition (ALD) of GST from GeCl2.C4H8O2, SbCl3, and Te[(CH3)3Si]2 on Si/SiO2 substrates, focusing on growth per cycle, morphology, and composition along with initial precursor reactions on the substrate. We found that while thick layers approach stoichiometric Ge2Sb2Te5, a Ge-rich interfacial layer is initially formed, regardless of the binary ALD sequence used to start the deposition (GeTe vs Sb2Te3). Starting the ALD process with the GeTe-Sb2Te3 sequence results in a higher Ge content near the GST/SiO2 interface compared to the Sb2Te3-GeTe sequence. To understand these phenomena, we examine the initial precursor reactions on the SiO2 substrate by total reflection x-ray fluorescence spectrometry. The analysis reveals that SbCl3 exhibits lower reactivity with the SiO2 substrate than GeCl2.C4H8O2, and not all Ge adspecies react with the Te[(CH3)3Si]2 precursors. Additionally, the impact of the initial SiO2 surface on deposition extends over several ALD cycles, as the SiO2 surface only gradually gets covered by GST due to island growth. These processes contribute to the formation of a Ge-rich GST layer at the interface, irrespective of the precursor pulse sequence. These insights from the study may contribute to optimizing the initial deposition stages of GST and other ternary ALD processes to enable better composition control and enhanced device performance.

Co/HfO2-based CBRAM stacks are optimized to enlarge the memory window for low-current (50 µA) operation. We dope the switching layer with Si to decrease the pristine current. First, we enlarge the memory window and reduce the forming voltage by scaling the Si-doped HfO2 thickness. Then, we extend the endurance lifetime and reduce the write time by introducing a hygroscopic oxide, LaSiO, in combination with HfSiO, to enhance Co ion hopping through hydroxyl groups. We further outline the important role of the position of the hygroscopic layer with respect to the Co active electrode in enlarging the memory window of the CBRAM device up to larger than105.

Area-selective deposition (ASD) is a bottom-up patterning technique that is of interest for nanoprocessing and next-generation semiconductor device manufacturing. This work demonstrates the great potential of dechlorosilylation chemistry for ASD through the example of Ge2Sb2Te5 (GST), a promising phase change material for storage class memory (SCM) applications. The fabrication of SCM devices may be facilitated by ASD as it involves complex nanoscale three-dimensional structures. We therefore investigate GST ASD on a TiN growth area with SiO2 as a nongrowth area. A selectivity of >0.9 is maintained up to similar to 45 nm of GST by using a single reaction of an aminosilane small molecule inhibitor in combination with GST atomic layer deposition (ALD) with GeCl2C4H8O2, SbCl3, and Te[(CH3)(3)Si](2) as precursors at 70 degrees C. The high selectivity is maintained for much thicker films compared to that of previously investigated ALD chemistries that use other precursors and O-2, H2O, or NH3 co-reagents in combination with the same inhibitor. Interestingly, the selectivity, the ideal 2:2:5 composition, and the amorphous phase of Ge2Sb2Te5 are maintained during ASD on SiO2/TiN line patterns with a half-pitch of 45 nm. A careful study of the growth evolution suggests that the growth mechanism for ASD on these nanopatterns relies on diffusion in addition to adsorption, indicating that diffusion-mediated selective deposition is not limited to metal ASD processes such as those of Ru and Pt. We propose that the combination of the ALD dechlorosilylation chemistry with passivation approaches including small molecule inhibitors creates a promising avenue for expanding the ASD material space to a wide range of new materials, enabling new applications for ASD in nanoelectronics, nanoprocessing, catalysis, etc.

In this work, the impact of a tungsten oxide (WO3) seed and capping layer for ferroelectric La-doped (Hf, Zr)O2 (La:HZO) based capacitors, designed with back-end-of-line (BEOL) compatibility, is systematically investigated. The WO3 capping layer supplies oxygen to the La:HZO layer throughout the fabrication process and during device cycling. This facilitates the annihilation of oxygen vacancies (Vo) within the La:HZO layer, thereby stabilizing its ferroelectric orthorhombic phase and resulting in an increase of the remanent polarization (Pr) value in the capacitor. Moreover, the effectiveness of the WO3 capping layer depends on the seed layer of the HZO film, suggesting that proper combination of the seed and capping layers should be employed to maximize the ferroelectric response. Finally, a TiN/TiO2 seed layer/La:HZO/WO3 capping layer/TiN capacitor is successfully fabricated and optimized by a complete set of atomic layer deposition (ALD) processes, achieving a superior 2Pr value and endurance value of more than 109 cycles at an electric field of 2.5 MV/cm. The WO3 capping layer is anticipated to offer a viable solution for doped HZO capacitors with reduced thickness, addressing the challenge of elevated Vo levels that favor the tetragonal phase and result in low 2Pr values.

In this paper, we develop a SiON layer with High-K incorporated (HKSiON) for tunnel oxide in a 3D-NAND gate stack. The objective is to improve the programming efficiency that tends to degrade with Z-pitch scaling, as well as with a possible transition from Gate All Around to Trench cells architecture. The results show that increasing the High-K content in a SiON tunnel layer leads to a significant reduction in programming voltage at the expense of retention, therefore causing a trade-off between these two parameters. Low High-K content however, can bring a distinct improvement in programming with limited retention penalty only.

In this paper, the kinetics of Ni metal induced lateral crystallization (MILC) in a Si channel has been thoroughly investigated. The impact of excess Ni supply, high-and-long thermal treatments, and fast ramp rate annealing on the quality of Si channel formed are reported. We show that it is possible to achieve up to 10 times higher mobility, and enhanced channel control with a controlled MILC process compared to a regular polysilicon channel.

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

We report on scaled Si-channel finFETs (Lgate>20nm, 45nm fin pitch) with backside connectivity enabled by: extreme wafer thinning (several Si thicknesses under STI-oxide targeted: from ~370nm down to ~20nm) and W-filled nano-through-Si-vias (n-TSV) of various heights (linked to wafer thinning values), after using low-temperature (LT), wafer-to-wafer (W2W) dielectric bonding. This scheme aims at allowing decoupling signal and power networks, with reduced IR-drop also predicted by moving the latter to the wafer’s backside. A thorough evaluation of the impact of 3D processing on device characteristics is presented, showing: 1) enhanced nmos mobility and drive currents (up to 15%); 2) for pmos, small ION loss (~3 to 10%), larger Rext, with channel strain evaluation by NBD for various layouts; 3) ΔVT~-130mV that can be recovered with an extra anneal at the end, keeping tight variability and matching control. No BTI degradation is observed, with further indication that the final anneal(s) selection can be beneficial for electrostatics and reliability improvement.

We thoroughly benchmark the reliability of Cu-based CBRAM stacks with different switching layers against state-of-the-art OxRAM stacks. We optimize the switching conditions for maximizing the endurance lifetime in three CBRAM stacks, outlining the impact of the switching layer on the energy required for the switching operation and on the memory window. We show that CBRAM provide a larger memory window than OxRAM, but the switching energy is systematically higher, and the endurance lifetime is shorter. We also demonstrate that the larger memory window of CBRAM degrades over time and is thus only an apparent advantage with respect to OxRAM. Therefore, this study reveals that OxRAM devices investigated in this work are more suitable candidates than for applications targeting long data retention and low programming voltage.

We demonstrate the integration of Ruthenium (Ru) and Molybdenum (Mo) as Word Line (WL) metals in a record 40nm pitch 3D-NAND device through an optimized Replacement Metal Gate (RMG) process. The optimized RMG process minimizes oxide regrowth which affects WL fill capability in reduced pitches. Ru and Mo gates show better resistivity (ρ) and memory characteristics compared to the currently used Tungsten WL. We demonstrate good channel control and program/erase (P/E) characteristics down to 20nm WL. Best P/E is obtained for Mo with 2nm HfOx liner after a post metallization anneal (PMA) at 750°C for 20mins, while devices with Ru WL show better retention.

Fabrication of stacked CMOS tiers in a 3D sequential integration requires development of low thermal budget process modules. High-quality SiO 2 interfacial layer (IL), obtained up to now only by high-temperature (≥850 °C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL's grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E' defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO 2 defects at low temperatures (100-300 °C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO 2 quality and reliability surpassing a 900 °C oxide.

Co/LaSiO conducting bridge random access memory is a promising candidate for low power storage class memories due to its high endurance and short switching pulse width. Moisture has been hypothesized to be an important parameter in determining device retention. In this study, we anneal the LaSiO layers at different temperatures and pressures in order to reduce the absorbed moisture and improve retention. We evidence by Fourier transform infrared and x-ray reflectivity that the moisture content does not change with these anneal conditions. However, we find that increasing the amount of La–OH bonds is an effective way to improve the low resistance state retention.

We demonstrate the integration of Ruthenium as Word Line metal in a 3-D NAND device by adopting the Replacement Metal Gate (RMG) process. Ruthenium gate shows better resistivity compared to currently used Tungsten and improved memory characteristics compared to what is obtained with a TiN electrode. Overall best performance is obtained with a 2 nm ZrO2 liner / Ru stack, followed by a 750 °C anneal.

We explore different ways to improve the quality of polysilicon channel in 3-D NAND flash devices to increase the current conduction. The analysis includes the formation of the device bottom junction ( benchmarking diffused vs. epitaxially grown source), the role of defect passivation, the role of the protection layer on channel crystallization and the impact of macaroni channel thickness on grain size and on transistor performance.