A compact quantum random number generator (QRNG) based on an array of Single Photon Avalanche Diodes (SPADs) is presented here. The main feature of the proposed chip is the capability to generate random numbers without the use of any external source of light. In this view, SPADs are configured to be used in two ways: 1) as a controlled light emitter and 2) as a detector. An embedded logic is able to distinguish dark events against detected emitted photon in such a way to make the system sensitive only to the presence of light. The extracted random bits show a uniform distribution and the QRNG, thanks to an integrated conditioning block maximizing the output entropy, eventually passes all AIS31 tests. The average raw bit rate in the default device configuration (one enabled column) is measured equal to 800 kbps.

This live demonstration shows a monolithic quantum random number generator (QRNG) fabricated in a 22-nm standard CMOS technology and based on the dark events generated by a Single-Photon Avalanche Diode (SPAD). The random number generator relies on a novel methodology for random bit extraction based on an on-the-fly median estimation of the inter-arrival times between consecutive events. Thanks to this self-adapting mechanism, the quality of the output sequence is kept constant regardless of the working conditions.

In this work we present a quantum random number generator (QRNG) based on Single-Photon Avalanche Diodes (SPADs) implemented in 22-nm CMOS technology. A new approach for quantum random number generation is presented, based on the median estimation of the times between pulses defined by endogenous generation processes. The proposed methodology allows for a random number generation efficiency near to one, as well as randomly generated strings of bits that pass common randomness tests without the need for post-processing. Thanks to the use of standard CMOS technology for both the detection and the logic, our QRNG is suitable for a highly scalable solution.

This paper addresses the complex behavior of Single-Electron Bipolar Avalanche Transistors (SEBATs) through a comprehensive modeling approach. TCAD simulations were used to analyze the behavior of the device during avalanche pulses triggered by electron injection. The simulations consider the avalanche process and charge flow and include the parasitic capacitances and resistances. A SPICE model is proposed using parameters extracted from the TCAD simulations. Both TCAD and SPICE simulations are validated against experimental results obtained on 150 nm CMOS devices and are employed to provide a clear understanding of the phenomena observed experimentally during SEBAT operation. The impact of parasitic elements on device operation is studied using simulations. This work enables the optimization of SEBAT devices and their integration in circuits for better signal-to-noise ratios, efficiency, and potential applications in sensing and digitizing low-level signals.

This work provides an in-depth analysis of a Single Electron Bipolar Avalanche Transistor (SEBAT) fabricated in a 150 nm CMOS process through TCAD simulations. The device has been integrated with a FET detector to achieve its primary objective of detecting THz waves. Moreover, valuable insights into the performance limitations of existing SEBAT design are demonstrated. Experimental measurements conducted on the transistor reveal inefficient generation of avalanche pulse counts if compared to the flux of injected electrons that motivate the creation of enhanced detector designs. The paper explores methods to significantly improve individual device performance through a comprehensive redesign of the SEBAT geometry and integration scheme.

This paper reports on a proof-of-concept SPAD-based (Single Photon Avalanche Diode) optical encoder. The work aims at demonstrating the advantages of SPADs over photodiodes, which are typically used in the current optical position measuring systems. In addition to their high sensitivity and high speed, SPADs allow fully digital signal processing, offering a large system flexibility and scalability toward advanced CMOS technologies. Preliminary tests have been carried out using an array of 100 x 100 SPADs, coupled with an optical Gray-coded disk and a laser diode. Binary frame sequences were acquired and processed off-line through a lightweight algorithm to reproduce the disc code. The described algorithm aims at being integrated in the same chip of the sensor to speed up the signal processing chain, thus allowing high rotation speeds to be achieved. Experimental results are reported, together with future work and conclusions.

While silicon industry advances to smaller and smaller feature sizes, silicon particle detectors struggle to follow that miniaturisation. One of the main bottlenecks are the relatively large transistors required for the optimal performance of the analogue frontend. Particam instead uses a digital-only approach which is focused on digital storage cells switching due to transient radiation (Single Event Upset (SEU)). Typically, great effort is expended to prevent SEUs from affecting the registers of any ASIC, but designs can also be optimised in the opposite way. With a pixel being little more than a memory cell it can be designed with close to minimum feature size with very few transistors allowing pixel pitches of a few microns. A proof-of-principle demonstrator with different pixel flavours with pitches ranging from 6.5 µm to 2 µm has been produced in the UMC 65 nm process. Test pulse measurements show the circuits work as intended, however the charge collection was found to be insufficient for most types of ionising radiation besides alpha particles. Results of this prototype are presented. Plans for further developments and possible applications are discussed.

The present paper describes a new QRNG based on the arrival time of photons. The device needs an external light source to fully control the generation of random bit. This allows to ensure an almost constant data rate, regardless possible environmental parameter variations, and a minimization of the contribution of other unwanted sources of noise (DCR). To increase the output rate, the QRNG is split up into several e lementary generators organized in an array working simultaneously. Moreover, an embedded post-processing block allows to improve the output entropy for a high quality random sequence. The device, now under test, has been designed in a standard 150nm CMOS technology. Preliminary results showed an average activity of about 30 Mbps (raw data).

In this paper we describe the architecture of a 256x256 Single Photon Avalanche Diode (SPAD) imager designed for quantum imaging applications in a 110nm CMOS Sensor Imaging process. The chip features a 256x256 SPAD array with 30 mu m pitch and reconfigurable pixel multi-functionality i.e. photon counting with fast gating mode or continuous time stamping of time correlated events with an external trigger. The array is organized in macro-pixels composed of clusters of 2x2 SPADs sharing the Time-to-Digital Converter (TDC), a logic arbiter circuit and other in-pixel circuitry reaching a remarkable. 22% Fill Factor despite the small pixel area. To optimize the usage of the available electronics, we designed an architecture which can share the in-pixel resources also among the neighboring macro-pixels laying on the same line. We split the chip in two independent halves with dedicated readout circuitry to improve the data throughput guaranteeing the possibility to sustain a maximum expected photon rate of 100 Mphotons/s impinging on the focal plane array. To this end, a row and a column zero-suppression logic circuit have been envisaged to save time during the matrix readout phase increasing the chip frame rate.

This article reports on a 500 x 500 pixel CMOS vision sensor allowing multiple regions of interest (RoIs) per frame with programmable and arbitrary number, size, and shape, aimed at minimizing the delivered data and at reducing the required amount of off-chip computation. In the proposed application, the center of mass (CoM) terms of the RoIs, computed by the sensor, are used to monitor the activity in some zones of the scene to switch the sensor to a pixel delivering mode, enabling high-level image processing upon request through an external processing platform. Anomalies are detected as changes in the x-y position of the CoM. The embedded CoM processor (CoMP) extracts the centroid terms of the selected subwindows, managing a maximum RoI size of 128 x 128 pixels. The parameters of each RoI are uploaded rowwise through a serial interface (SI). The sensor with 8-mu m pixel pitch is manufactured in a 110-nm 1P4M CMOS technology and occupies 25 mm(2). The chip, operating in standard imaging mode (IM), consumes 4.9 mW at 20 fps.

This paper reports on a 500 x 500 pixel CMOS image sensor allowing multiple Regions of Interest (RoI) per frame with programmable number and size, aimed at minimizing the amount of data to be delivered off-chip and at reducing its power consumption. The proposed sensor architecture offers large flexibility to face different use case scenarios and it is suitable to any pixel array. The sensor embeds image background subtraction capability and integrates a computing layer which pre-filters the pixels to estimate the Center of Mass (CoM) of the RoIs up to a maximum size of 128 x 128 pixels. The 8 $\mu \mathrm{m}$ pixel sensor is manufactured in a 110 nm 1P4M CMOS technology and occupies 25 $\mathrm{m}\mathrm{m}^{2}$. The chip, operating in standard imaging mode, consumes 4.9 mW at 30 fps.

A compact quantum random number generator based on an array of Single Photon Avalanche Diode (SPAD) is presented here.As the main feature, the proposed chip has the capability to generate random numbers without the use of an external source of light.In the present approach, SPAD devices are used as emitters and as detectors.An embedded logic allows distinguishing dark events from events coming from the photon emission.The extracted random bit sequence shows a quite uniform distribution and after being post-processed by means of an integrated circuit, used to maximize the entropy of the system, is able to pass the AIS31 test.The average bit rate is 400 kbps.

The present paper shows possible ways to design monolithic Quantum Random Number Generators ( QRNGs) in a standard CMOS technology. While all commercial QRNGs based on SPAD technology use an external light as main source of entropy, in the present implementation silicon-based photon sources are used. This approach allows the integration of monolithic QRNGs paving the way towards miniaturized and low-cost devices. Moreover, being the QRNG realized in a standard CMOS technology, in perspective, it can potentially be embedded in secure microprocessor. In the paper we show that the proposed approach is compact, produces a minimum event rate of about 1kHz, possibly extended in case of the implementation of multi-QRNGs working in parallel.

In the presented paper we describe an innovative pixel topology designed for particle tracking. The proposed approach is based on a fully digital concept. When ionising particles traverse detector material, charges collected by the pixel are converted to a single bit to obtain a binary image. This digital approach allows a simplified pixel schematic to be used, reducing the pixel size to 2.5 μm × 2.5 μm and optimises the power consumption and the speed of the readout. An array of 256×256 pixels have been fabricated in a 65 nm standard CMOS technology as a proof of concept. Preliminary results on pixel performance are reported, demonstrating the potential of the approach.

A SPAD-based pixel with a single transistor has been designed and implemented in a 150nm standard CMOS technology for the realization of a Quanta Image Sensor (QIS). The inherently digital nature of the SPAD device minimizes circuitry and simplifies the achievement of singlephotoelectron sensitivity. The pixel revamps the concept of CMOS passive-pixel sensors to achieve a pixel with a pitch of 7m and a geometrical fill-factor of 31% in an unoptimized process. The speed of the presented QIS architecture is limited only by the output interface, while requiring extremely simple column circuitry such as a sense amplifier, thus minimizing power requirements.

Secondary neutrons produced in particle therapy (PT) treatments are responsible for the delivery of a large fraction of the out-of-target dose as they feebly interact with the patient body. To properly account for their contribution to the total dose delivered to the patient, a high precision experimental characterisation of their production energy and angular distributions is eagerly needed. The experimental challenge posed by the detection and tracking of such neutrons will be addressed by the MONDO tracker: a compact scintillating fiber detector exploiting single and double elastic scattering interactions allowing for a complete neutron four-momentum reconstruction. To achieve a high detection efficiency while matching the fiber (squared, 250 mu m side) high granularity, a single photon sensitive readout has been developed using the CMOS-based SPAD technology. The readout sensor, with pixels of 125 x 250 mu m(2) size, will be organised in tiles covering the full detector surface and will implement an autotrigger strategy to identify the events of interest. The expected detector performance in the context of neutron component characterisation in PT treatments delivered using carbon ions has been evaluated using a Monte Carlo simulation accounting for the detector response and the neutrons production spectra.

In this letter, a stitched array of 768×64 pixels for X-ray dental imaging is presented. The sensor architecture allows to increase the frame rate up to 900 fps thanks to a pipeline approach that minimizes the deadtime between consecutive frames. A column-based ADC converts pixel values in digital form while an external FPGA performs the operation of time-delay integration accumulation, thus increasing the signal-to-noise ratio. Internal programmable gain allows to achieve a maximum sensitivity of 2.6 LSB/nGy and, at the same time, to extend the dynamic range of the sensor in case of high intensity. The final system consists of two sensors each one having a size of 74.5×9 mm, assembled in a PCB and coupled with a high sensitive columnar thallium-doped cesium iodide (CsI(Tl)) scintillator for X-ray conversion. The sensor, fabricated in a standard CMOS 0.15-μm technology with a stitching approach, shows a pixel size of 97 μm.

This article reports the design and characterization of a 32 $\times $ 32 single-photon avalanche diode (SPAD) time-resolved image sensor for quantum imaging applications fabricated in a 150-nm CMOS standard technology. A per-SPAD time-to-digital converter (TDC) records the spatial cross correlation functions of a flux of entangled photons. Each 44.64- $\mu \text{m}$ pixel with 19.48% fill-factor features a 210.2-ps resolution, 50-ns (8-bit) range TDC with 1.28-LSB differential and 1.92-LSB integral nonlinearity (DNL/INL). The sensor achieves an observation rate of up to 1 MHz through a current-based mechanism that avoids reading empty frames when the photon rates are low. A row-skipping mechanism detects the absence of SPAD activity in a row to increase the duty cycle. These two features require only three transistors in each pixel. The sensor functionality is demonstrated in a quantum imaging experiment that achieves super-resolution.