To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm 2. The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.

On the one hand, processors for hearing aids are highly specialized for audio processing, on the other hand they have to meet challenging hardware restrictions. This paper aims to provide an overview of the requirements, architectures, and implementations of these processors. Special attention is given to the increasingly common application-specific instruction-set processors (ASIPs). The main focus of this paper lies on hardware-related aspects such as the processor architecture, the interfaces, the application specific integrated circuit (ASIC) technology, and the operating conditions. The different hearing aid implementations are compared in terms of power consumption, silicon area, and computing performance for the algorithms used. Challenges for the design of future hearing aid processors are discussed based on current trends and developments.

Choosing a suitable processor architecture for a hearing aid is a difficult task. Various aspects have to be taken into account, like power consumption and silicon area. Also, the computational performance and flexibility of an architecture are essential. Therefore, a wide variety of design goals must be weighted against each other before a final decision for the architecture can be made. In this paper, several configurable audio processors are evaluated, using five commonly known acoustic beamforming algorithms. In order to reduce the exploration time, this paper presents a partly automated design space exploration framework. The hearing aid algorithms are implemented in fixed-point representation to reduce the computational complexity. This framework includes a fixed-point analysis and an automated reference code generation using MATLAB tools. With the Xtensa Xplorer, different configurations of the Tensilica-based processor architecture are profiled. Finally, a case study is presented to show the usability of the proposed framework.

Code generation for VLIW processors includes several optimization problems like code optimization, instruction scheduling, and register allocation. The high complexity of these problems usually does not allow the computation of the optimal solution. Instead, optimization techniques, e.g., based on heuristics, are used to find acceptable solutions in a reasonable time. List scheduling is a well known heuristic-based microcode compaction method, that bases its scheduling decisions on weights derived from dependency analysis of the input program. Additional information and methods have to be used in order to reach better code compaction. Also, more sophisticated code optimization and register allocation support better code compaction. In this paper, evolutionary algorithms are used as dynamic heuristics in code generation, which allows dynamic adaption to the given input program and target processor configuration. Three evolutionary algorithms for operation merging, instruction scheduling, and register allocation are presented and evaluated on an exemplary image processing application, which shows different processing characteristics in the subroutines. They outperform code generation based on static heuristics and allow compilation for restricted target architectures that cannot be handled by the static heuristics.

Predication is a well-known alternative to conditional branching. However, the implementation of predication is costly in terms of extending the instruction set of the processor architecture. In this paper, a predication encoding technique for VLIW processors is proposed. Instead of using additional bits in the instruction encoding, the assigned issue-slot of a conditionally executed instruction encodes the associated predicate register. The number of addressable predicate registers scales with the number of issue-slots. All predicate registers have only one read and write port and can be accessed in parallel. Compared to the related work, no additional instruction encoding bits for selecting a predicate register are required and the processor core area increases only by about 1% per predicate register set. With the proposed predication technique, the processing performance increases by up to 4.5% when using two instead of one predicate register for a digital filter case study with floating-point emulation operations. A second case study shows, that conditional execution with two predicate register in combination with loop unrolling and operation merging almost doubles the achieved parallel instructions per cycle for a bit-reversal permutation algorithm.

The integration of application specific instruction set processors (ASIPs) in hearing aids requires various architectural customizations and software-side optimizations in order to meet the stringent power consumption constraints and processing performance demands. This paper presents the KAVUAKA application specific hearing aid processor and its ASIC integration as a system on chip (SoC). The final system contains four KAVUAKA processor cores and ten co-processors. Each of these processors and co-processors were individually customized and differ in their data path width. The processors are organized in two clusters, which share memories, an audio interface, co-processors and a serial interface. With this system, different hearing aid systems are evaluated in terms of performance, power and area by activating different processor and co-processor combinations. A 40nm low power technology was used to build this research hearing aid system. The die size is 3.6mm(2) with less than 1mm(2) per core. The measured average power consumption is less than 1mW per core.

In several applications of machine listening, predicting how well an automatic speech recognition system will perform before the actual decoding enables the system to adapt to unseen acoustic characteristics dynamically. Feedback about speech quality, for instance, could allow modern hearing aids to select a speech source in complex acoustic scenes with the aim of enhancing the speech intelligibility of a target speaker. In this study, we look at different performance measures to estimate the word error rates of simulated behind-the-ear hearing aid signals and detect the azimuth angle of the target source in 180-degree spatial scenes. These measures derive from phoneme posterior probabilities produced by a deep neural network acoustic model. However, the more complex the model is, the more computationally expensive it becomes to obtain these measures; therefore, we assess how the model size affects prediction performance. Our findings suggest measures derived from smaller nets are suitable to predict error rates of more complex models reliably enough to be implemented in hearing aid hardware.

In this paper, the effects of application-specific instruction-set processor (ASIP) hardware optimizations on the performance of beamforming algorithms and on the hardware requirements (i.e., silicon area and power consumption) are studied. For that, the performance of three beamforming algorithms with different fixed-point implementations are compared using objective instrumental measures, i.e., PESQ, STOI, and iSNR. The proposed application-specific hardware optimizations are implemented in a VLIW-SIMD hearing aid processor, modifying the processor's datapath width, using a co-processor for the division operation and applying register file power optimizations. In total 24 different optimized processor configurations are studied. The result of this evaluation is that the same processor, running one of the beamformers, can be optimized, decreasing up to 2 times the silicon area requirements or up to 11 times the power consumption, thereby only slightly decreasing the overall algorithm performance (e.g., −2dB iSNR for a fixed beamformer).

Instruction scheduling and register allocation for VLIW architectures are complex problems for which computing the optimal solution is often infeasible. Instead, optimization techniques and heuristics are used to find good solutions in reasonable time. List scheduling is a well known microcode compaction method, which uses weights derived from data dependency graphs of the input program in its heuristic function. Additional information and mechanisms have to be used in order to reach better code compaction. In this paper, a genetic algorithm is used to tune the heuristics during list scheduling, which allows dynamic adaption of the algorithm to the given input program. The genetic scheduler often outperforms list scheduling with static heuristic and handles situations with register file pressure that might be impossible to schedule with the heuristic based list scheduling. A second genetic algorithm is proposed to perform X2 operation merging, a code optimization step exploiting special execution mode of the target hardware architecture.

Localization algorithms have become of considerable interest for robot audition, acoustic navigation, teleconferencing, speaker localization, and many other applications over the last decade. In this paper, we present a real-time implementation of a Gaussian mixture model (GMM) based probabilistic sound source localization algorithm for a low-power VLIW-SIMD processor for hearing devices. The algorithm has been proven to allow for robust localization of multiple sound sources simultaneously in reverberant and noisy environments. Real-time computation for audio frames of 512 samples at 16 kHz was achieved by introducing algorithmic optimizations and hardware customizations. To the best of our knowledge, this is the first real-time capable implementation of a computationally complex GMM-based sound source localization algorithm on a low-power processor. The resulting estimated core area without consideration of memory in 40nm low-power TSMC technology is 188,511 pm 2 .

ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. For an exemplary timing analysis campaign of an existing chip design, speed-up factors of up to 267 are achieved while maintaining timing behavior deviations lower than 1.05% to timing simulations.

In this paper, a software floating-point emulation library for fixed-point SIMD processors is proposed. The single instruction multiple data (SIMD) mechanism of those processors is exploited in this work to efficiently emulate fast software floating-point operations. The key feature of this approach is the independent processing of the significand and the exponent, stored in different sized subwords of one SIMD word. Additional processing performance is obtained by computing multiple floating-point operations in parallel using one SIMD instruction. Compared to related work, no additional hardware overhead is required to speed up the software emulation of floating-point arithmetic. An evaluation of fixed-and floating-point signal processing algorithms, implemented on a fixed-point VLIW-SIMD processor, shows the differences in performance, precision, and code size.

This paper explores a real- and complex-valued multiply-accumulate (MAC) functional unit for digital signal processors. MAC units with single-instruction-multiple-data (SIMD) support are often used to increase the processing performance in modern signal processing processors. Compared to a real-valued SIMD-MAC units, the proposed unit uses the same multipliers to also support complex-valued SIMD-MAC and butterfly operations. The area overhead for the complex mode is small. Complex-valued operations speed up signal processing algorithms and make the execution more efficient in terms of power consumption. As a case study, a fast Fourier transform (FFT) is implemented for a VLIW-processor with a complex-valued SIMD butterfly extension. The proposed functional unit is quantitatively evaluated in terms of performance, silicon area, and power consumption.

Research of efficient fault tolerance techniques for digital systems requires insight into the fault propagation mechanism inside the ASIC design. Radiation, high temperature, or charge sharing effects in ultra-deep submicron technologies influence fault generation and propagation dependent on die location. The proposed methodology links efficient fault injection to fault propagation in the floorplan view of a standard cell ASIC. This is achieved by instrumentation of the gate netlist after place&route, emulation in an FPGA system and experiment control via interactive user interface. Further, automated fault injection campaigns allow exhaustive fault tolerance evaluations taking single faults as well as adjacent cell faults into account. The proposed methodology can be used to identify vulnerable cell nodes in the design and allow the classification of placement strategies of fault tolerant ASIC designs.

Hardware architectures for modern hearing aid devices have to provide ultra low power consumption at a small silicon area and moderate computational performance to deal with the continuously growing complexity of hearing aid signal processing. At the same time, they need to remain flexible for future algorithmic changes. These challenging design goals can be achieved by using Application-Specific Instruction-Set Processors (ASIPs), where a baseline architecture is customized to the target class of applications. In this paper, hardware modifications of a generic VLIW-SIMD processor architecture targeting audio processing are described and their influence in area-performance efficiency and power are evaluated. As exemplary hearing aid signal processing application, the evaluated algorithms contain a complex modulated filter bank and a noise reduction algorithm. The proposed architecture requires 2 times less silicon area and a 6 times lower clock frequency than a Tensilica Xtensa LX4 when running the same algorithms under real-time conditions.