A comprehensive design optimization methodology using intuitive nondimensional parameters of inversion-level and saturation-level is proposed, especially for ultralow-power, low-voltage, and high-performance analog circuits with mixed strong, moderate, and weak inversion metal–oxide–semiconductor transistor (MOST) operations. This methodology is based on the synthesized charge-based MOST model composed of Enz–Krummenacher–Vittoz (EKV) basic concepts and advanced-compact-model (ACM) physics-based equations. The key concept of this methodology is that all circuit and system characteristics are described as some multivariate functions of inversion-level parameters, where the inversion level is used as an independent variable representative of each MOST. The analog circuit design starts from the first step of inversion-level design using universal characteristics expressed by circuit currents and inversion-level parameters without process-dependent parameters, followed by the second step of foundry-process-dependent design and the last step of verification using saturation-level criteria. This methodology also paves the way to an intuitive and comprehensive design approach for many kinds of analog circuit specifications by optimization using inversion-level log-scale diagrams and saturation-level criteria. In this paper, we introduce an example of our design methodology for a two-stage Miller amplifier.

We have proposed a single metal/dual high- k gate stack for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high- k dielectrics, such as MgO- and Al 2 O 3 -containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.

We have investigated the effect of postdeposition annealing (PDA) of Al2O3-capped HfO2 films on the flatband voltage (V-fb) shift and threshold voltage (V-t) variation in TiN gate p-type metal-insulator-semiconductor field-effect transistors (pMISFETs). We found that optimizing the PDA conditions to diffuse Al2O3 into the HfO2 films is a key factor for controlling V-fb, and high-temperature PDA immediately after Al2O3 deposition induces a positive V-fb Shift. Additional V-t variation was observed when the PDA temperatures after Al2O3 deposition were 850 and 950 degrees C. In contrast, a higher temperature PDA at 1050 degrees C after Al2O3 deposition can suppress V-t variation to almost the same level as that obtained in a HfO2 film without an Al2O3-cap layer, although the equivalent oxide thickness (EOT) increases. We also found that superior device characteristics, such as low V-t, suppression of V-t variation, and suppression of EOT increase, were obtained by performing PDA before Al2O3 deposition. (C) 2009 The Japan Society of Applied Physics

In this paper, we describe a new technique of enhancing hole mobility in full-metal high-k p-channel field effect transistors (pFETs) constructed by a conventional gate-first process. A tungsten layer used as a low-resistivity gate creates a global tensile strain when it is deposited by physical vapor deposition (PVD). After the gate patterning, however, the stress in the tungsten gate modulates the local strain in the channel. If it is deposited by ion-beam PVD, the tungsten layer has a small amount of compressive stress, and does not relax the wafer-level global strain created in the W-deposition step, and eventually creates a local tensile strain after gate patterning in the horizontal (source-to-drain) and vertical (gate-to-substrate) directions. In contrast, if it is deposited by conventional PVD, the large amount of compressive stress in the tungsten gate creates a small amount of local compressive strain in the horizontal and vertical directions after gate patterning. Since the vertical tensile strain created by the ion-beam-deposited tungsten gate increases the drain current of pFETs, it can be used as a cost-effective stress memorization technique to enhance device performance.

Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.

We have investigated the impacts of the nitrogen content in a TaSiNx metal gate on the performance of metal/HfSiON n-type field-effect transistors (FETs). To obtain a low threshold voltage and low electrode resistance, low nitrogen concentration in TaSiNx is preferable. However, the use of a TaSi gate ([N] = 0%) causes the degradation of HfSiON dielectric characteristics such as an increase in leakage current under gate negative bias, positive-bias temperature instability lifetime degradation, time-dependent dielectric breakdown lifetime degradation, and reduction of the electron mobility. Then, a low-nitrogen-concentration TaSiN ([N] = 20%) gate shows the highest electron mobility, excellent reliability characteristics, and low threshold voltage.

Three SiN offset spacers were compared regarding the suppression of the gate-edge metamorphoses (GEMs) of scaled TaSiN/HfSiON n-type metal-oxide-semicondutor field-effect-transistors. The offset-spacer-induced GEM appears only in short-channel devices as a high threshold voltage (V(th)) and a parasitic resistance. On the basis of the device characteristics, the origin of GEMs was hypothesized to be the negative fixed charge in HfSiON on the gate edges. The low-temperature, Cl-free SiN offset spacer is promising for use in scaled metal/high-k devices because it provides the lowest Vth and the highest drivability, particularly in short-channel devices, by suppressing GEMs.

This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (V TH ) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low V TH values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of V TH roll-offs and I on -I off 's if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated.

We will give practical and manufacturable solutions for metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.

2008 International Conference on Solid State Devices and Materials,Vt Variation Suppressed Al2O3-Capped HfO2 Gate Dielectrics for Low Vt pMISFETs with High-k/Metal Gate Stacks

We investigated the controversial effective workfunction and electron mobility of TiN/HfSiON devices by intentionally adding MgO or La2O3 into HfSiON and by changing the material on TiN or the TiN thickness. As a result, we found a close relationship between the electron mobility at low effective field and the flatband voltage. This relationship is explained on the basis of the fixed charge in HfSiON and its neutralization. The intrinsic workfunction of TiN/HfSiON without charge is determined to be 4.3 eV from the flatband voltage when the electron mobility at low effective field is the highest. [DOI: 10.1143/JJAP.47.7780]

This paper describes the applications of cluster ion implantation for beyond 45 nm node novel devices. A) Metal/high-k MOSFET: a flash lamp annealing (FLA) has advantage of dopant diffusion-less characteristics, but it requires suitable angle control for optimum gate overlap length. Cluster boron implantation with tilted SDE implantation for p-FETs has superiority over monomer boron implantation with Ge PAI (pre-amorphous implantation) in terms of VTH roll-off s and ion-ioff s if FLA is used as activation anneal. Full-metal-gate HfSiON transistors whose gate length is less than 50 nm are fabricated with superior electrical characteristics. B) n-MOS stress engineering: Si:C formation with high carbon substitution has been obtained using cluster carbon implantation and msec annealing which leads to higher stress in the channel region. C) Fin-FET: high tilt angle with low energy boron cluster ion implantation is found to improve the retained dose compared to monomer boron. It is suitable for Fin-FET implantation applications.

We clarified the impact of the fifth material incorporation into HfSiON technology for Vth control on the reliability of high-k/metal gate stacks CMOSFETs. HfMgSiON is remarkably effective for suppressing electron traps, giving rise to a dramatic PBTI lifetime improvement for nMOSFETs. With pMOSFETs, Al incorporation is effective for the thermal deactivation of hole traps, resulting in NBTI lifetime improvement. We have established the guidelines of material selection to be incorporated into HfSiON for reliability improvement for nMOS and pMOS individually.

We have proposed single metal/dual high-k (SMDH) CMISFETs for aggressively scaled devices. The low threshold voltage (Vth) for n- and pMISFETs are obtained by the dual high-k gate dielectrics. The common gate stack for n- and pMISFETs (single metal) is expected to suppress the variation of gate profile. We have successfully demonstrated low-Vth operation of TiN/HfMgO nMISFETs and TiN/HfAlO pMISFETs that were fabricated in a gate first process flow. We also investigated the high-k-induced Vth variation that can be another origin of the Vth variation. As a result, we found that TiN/HfMgO nMISFETs and TiN/HfAlO pMISFETs do not suffer from high-k-induced Vth variation, but that TiN/HfLaO nMISFETs fabricated by our current process suffer from it. Therefore, we need to optimize the La incorporation process, such as, post-deposition anneal, in order to suppress local high-k-induced Vth variation for TiN/HfLaO nMISFETs.

The motions of particles are calculated in 3D structure to evaluate potential fluctuation. The results of homogeneous and thermal equilibrium systems are in good agreement with theoretical results. In 3D MOSFET, the potential fluctuation extends towards the depletion layer and deviation of the amplitude from theoretical value is observed and ascribed to hot electron energy distribution, so the conventional plasmon scattering model should be modified in non-uniform and non-equilibrium carrier distribution.