Tunnel Field Effect Transistors (FETs) have the potential to achieve steep Subthreshold Swing (S.S.) below 60 mV/dec, but their S.S. could be limited by trap-assisted tunneling (TAT) due to interface traps. In this paper, the effect of trap energy and location on OFF-current (IOFF) of tunnel FETs is evaluated systematically using an atomistic trap level representation in a full quantum transport simulation. Trap energy levels close to band edges cause the highest leakage. Wave function penetration into the surrounding oxide increases the TAT current. To estimate the effects of multiple traps, we assume that the traps themselves do not interact with each other and as a whole do not modify the electrostatic potential dramatically. Within that model limitation, this numerical metrology study points to the critical importance of TAT in the IOFF in tunnel FETs. The model shows that for Dit higher than 1012/(cm2 eV) IOFF is critically increased with a degraded ION/IOFF ratio of the tunnel FET. In order to have an ION/IOFF ratio higher than 104, the acceptable Dit near Ev should be controlled to no larger than 1012/(cm2 eV).

A high performance triple-heterojunction (3HJ) design has been previously proposed for tunneling FETs (TFETs). Compared with single HJ TFETs, the 3HJ TFETs have both shorter tunneling distance and two transmission resonances that significantly improve the ON-state current ( ${I}_{\scriptscriptstyle {\text {ON}}}$ ). Coherent quantum transport simulation predicts that ${I}_{\scriptscriptstyle {\text {ON}}} = 460~\mu \textsf {A}/\mu \textsf {m}$ can be achieved at gate length $\text {Lg} = 15~\textsf {nm}$ , supply voltage ${V}_{\textsf {DD}} = 0.3~\textsf {V}$ , and OFF-state current ${I}_{\scriptscriptstyle {\text {OFF}}} = 1~\textsf {nA}/\mu \textsf {m}$ . However, strong electron–phonon and electron–electron scattering in the heavily doped leads implies that the 3HJ devices operate far from the ideal coherent limit. In this paper, such scattering effects are assessed by a newly developed multiscale transport model, which combines the ballistic nonequilibrium Green’s function method for the channel and the drift-diffusion scattering method for the leads. Simulation results show that the thermalizing scattering in the leads both degrades the 3HJ TFET’s subthreshold swing through scattering-induced leakage and reduces the turn-ON current through the access resistance. Assuming bulk scattering rates and carrier mobilities, the ${I}_{\scriptscriptstyle {\text {ON}}}$ is dropped from $460~\mu \textsf {A}/\mu \textsf {m}$ down to $254~\mu \textsf {A}/\mu \textsf {m}$ , which is still much larger than the single HJ TFET case.

GaSb/InAs heterojunction tunnel FETs are strong candidates in building future low-power ICs, as they could provide both steep subthreshold swing and large on-state current (I-ON). However, at short-channel lengths, they suffer from large tunneling leakage originating from the small bandgap and small effective masses of the InAs channel. As proposed in this paper, this problem can be significantly mitigated by reducing the channel thickness, meanwhile retaining a thick source-channel tunnel junction, thus forming a design with a nonuniform body thickness. Because of the quantum confinement, the thin InAs channel offers a large bandgap and large effective masses, reducing the ambipolar and source-to-drain tunneling leakage at off-state. The thick GaSb/InAs tunnel junction, instead, offers a low tunnel barrier and small effective masses, allowing a large tunnel probability at on-state. In addition, the confinement-induced band discontinuity enhances the tunnel electric field and creates a resonant state, further improving I-ON. Atomistic quantum transport simulations show that ballistic I-ON = 284 A/m is obtained at 15-nm channel length, I-OFF = 1 x 10(-3) A/m, and V-DD = 0.3 V, while with uniform body thickness, the largest achievable I-ON is only 25 A/m. Simulations also indicate that this design is scalable to sub-10-nm channel length.

VLSI devices are constrained by CF dd 2 /2 power dissipation. Low power dissipation requires low V dd , yet reducing V dd increases I off . Tunnel FETs (TFETs) have steep subthreshold swings (S.S.) and can operate at low V dd , yet their I on is limited by low tunneling probability. This low I on results in large CV dd /I delay and slow logic operation. For greatly increased Ion, we had proposed a triple-heterojunction (3HJ) TFET design incorporating source and channel heterojunctions (HJ) [1, 2]. The designs of [1, 2] have an InAlAsSb channel, yet no low-trap-density dielectric interfaces to InAlAsSb have been reported. In contrast, low-trap-density dielectric interfaces have been demonstrated to InAs, InGaAs, and InP [3, 4, 5]. Here we propose an InGaAs/GaAsSb/InAs/InP 3HJ TFET design, with growth lattice-matched to InP. The gated channel surface is InAs and InP, and thus can have low trap density. The p-type side of the tunnel junction is GaAsSb, instead of strained GaSb [6], as compressive strain increases the hole transport effective mass, reducing the tunneling probability. In ballistic simulations, with I off = 10 3 μA/μm and V dd =0.3V, I on is an extremely high 540μA/μm. Even when simulated assuming incoherent quantum transport, with acoustic and optical phonon scattering modelled, I on remains very high at 250μA/μm.

We propose a series of ultra-high-current triple-heterojunction (3HJ) tunnel field-effect transistor (TFET) designs based on InGaAs/InP materials. Such materials are Sb- and Al-free for ease of processing and to permit low-trap-density dielectric interfaces. Quantum transport simulations, based on eight-band kp Hamiltonian, considering effects of strain and electron-phonon scattering, are performed to guide the design and predict the device performance. With VDD=0.3V and IOFF=1nA/μm, the best design can achieve ballistic ION of 605μA/μm and, with electron-phonon scattering modeled at 310eV/nm optical deformation constant, a still-high 392μA/μm.

A triple-heterojunction (3HJ) design is employed to improve p-type InAs/GaSb heterojunction (HJ) tunnel FETs. Atomistic quantum transport simulations show, that the added two HJs (AlInAsSb/InAs in the source and GaSb/AlSb in the channel) significantly shorten the tunnel distance and create two resonant states, greatly improving the ON state tunneling probability. Moreover, the source Fermi degeneracy is reduced by the increased source (AlInAsSb) density of states and the OFF state leakage is reduced by the heavier channel (AlSb) hole effective masses. With VDD = 0.3V and IOFF = 1nA/μm, ballistic ION of 606μA/μm (492μA/μm) is obtained at 30nm (15nm) channel length, which is comparable to n-type 3HJ counterpart and significantly exceeding p-type silicon MOSFET. Simultaneously, the nonlinear turn on and delayed saturation in the output characteristics are also greatly improved.

Strain has been widely used to engineer electronic devices by altering the material band structures. Recently it has also been employed to improve the performance of tunneling field-effect transistors (TFETs). A TFET is a steep subthreshold swing (SS) device that is very promising in building future low-power integrated circuits. But its drive current (I ON ) is usually limited leading to pronounced switching delay (CV/I). It has been shown that for InAs nanowire TFETs, strain can reduce the band gap and/or effective masses leading to improved I ON . We show that for the experimentally more favorable ultra-thin-body (UTB) InAs TFETs, certain types of strain improve I ON when channel length is long (30 nm). When channel length is short (15 nm), however, the improvement is marginal due to degraded SS as a result of increased ambipolar leakage. To mitigate this detrimental effect, we propose to apply the strain locally in an area around the source-channel tunnel junction. Since the band structures of the channel and the source remain unaffected, the ambipolar leakage does not increase and meantime the source Fermi degeneracy is removed. In this way we obtain a significant boost of SS and I ON . The simulations are performed by solving Poisson equation and open-boundary Schroedinger equation self-consistently within NEMO5 tool. The band structure of III-V materials is described by strained eight-band k·p Hamiltonian. Since tunneling current is very sensitive to band structures, we extract the k·p band parameters and deformation potentials from the corresponding atomistic tight binding calculations, whose parameters are fit to first-principles density functional theory (DFT) calculations with excellent match. We compare the confined band structures as well as I-V curves obtained from both methods and show that the accuracy of the k·p method is guaranteed.

We report the design and simulated performance of a GaAsSb/GaSb/InAs/InP n-type triple heterojunction (3-HJ) tunnel field-effect transistor (TFET). GaAsSb/GaSb source and InAs/InP channel HJs both increase the field imposed upon the tunnel junctions and introduce two resonant bound states. The tunneling probability, and hence the transistor on-current, are thereby greatly increased. The devices were simulated using a non-equilibrium Green function quantum transport approach and the k.p method within NEMO5. With 10(-3) A/m (I-OFF) and a 0.3 V power supply V-DD, we simulate 380 A/m ON-current (I-ON) at 30-nm gate length (L-g) and 275 A/m at 15-nm L-g. Unlike a previously-reported high-current AlGaSb/GaSb/InAs/InGaAsSb 3-HJ design, the GaAsSb/GaSb/InAs/InP design employs channel materials to which high-quality, low-interface-state-density gate dielectrics have been demonstrated.

Future VLSI devices will require low CVdd2/2 switching energy, large on-currents (Ion), and small off-currents (Ioff). Low switching energy requires a low supply voltage Vdd, yet reducing Vdd typically increases /off and reduces the Ion/Ioff ratio. Though tunnel FETs (TFETs) have steep subthreshold swings and can operate at a low Vdd, yet their Ion is limited by low tunneling probability. Even with a GaSb/InAs heterojunction (HJ), given a 2nm-thick-channel (001)-confined TFET, [100] transport, and assuming Vdd=0.3V and IoFF=10-3A/m, the peak tunneling probability is <;3 % (fig. 1 a) and Ion is only 24 A/m (fig. 1b) [1]. This low Ion will result in large CVdd/I delay and slow logic operation. Techniques to increase /on include graded AlSb/AlGaSb source HJs [2,3] and tunneling resonant states [4]. We had previously shown that tunneling probability is increased using (11 0) confinement and channel heterojunctions [1], the latter increasing the junction built-in potential and junction field, hence reducing the tunneling distance. Here we propose a triple heterojunction TFET combining these techniques. The triple-HJ design further thins the tunnel barrier to 1.2 nm, and creates two closely aligned resonant states 57meV apart. The tunneling probability is very high, >50% over a 120meV range, and the ballistic Ion is extremely high, 800A/m at 30nm Lg and 475 A/m at 15nm Lg, both with Ioff=10-3 A/m and Vdd=0.3 V. Compared to a (001) GaSb/InAs TFET, the triple-HJ design increases the ballistic /on by 26:1 at 30nm Lg and 19:1 at 15nm Lg. The designs may, however, suffer from increased phonon-assisted tunneling.

Future high-performance low-power integrated circuits require compact logic devices with both steep subthreshold swing (SS) and large drive current (I ON ). Tunneling field-effect transistors (TFETs) can meet the first requirement but their I ON is severely limited either by the low source-channel tunneling probability or by the high source-to-drain tunneling leakage. One of the methods that can be employed to boost I ON is doping engineering. In particular (1)lowering the drain doping density elongates the drain depletion region and thus suppresses the leakage leading to improved SS (and ION). This scheme, however, is not scalable as a long drain length is needed to reach charge neutrality; (2) embedding an opposite N+ doping layer next to the P+ source, i.e., the source-pocket (SP) design, or inserting a δ doping layer, can enhance the electric field at the source-channel tunnel junction and improve ION. It can be shown that the improvement increases as the pocket doping density (Np) increases, but in practice doping density has an upper limit. In this paper, we show that, (1) embedding a P+ drain pocket can also improve the SS (and ION) and it is more scalable than lowering the drain doping; (2) by resorting to P+ channel, we can further improve I ON of the SP design without having to increase N p .

The downscaling of electronic devices has reached a regime where quantum and atomistic effects govern the active part of the device while semi-classical physics still plays a very important role for the remaining parts. A multiscale transport simulation approach is therefore developed in NEMO5 tool to address this issue. In this approach, nonequilibrium Green's function (NEGF) equations with atomistic tight-binding Hamiltonian are employed to calculate the ballistic current through the tiny central device, while drift-diffusion (DD) equations (with quantum charge density) are used to model the surroundings where scattering and relaxation dominate. These two sets of equations are coupled through quasi-Fermi levels, which are determined by continuity equation. With Poisson equation solved self-consistently, device characteristics such as the I-V curves are obtained. Using this approach we demonstrate two examples. For the first example, we consider a recently fabricated nitride tunneling diode that consists of a GaN-InNGaN heterojunction. The band-to-band tunneling through the strained heterojunction is accurately modeled by the NEGF method while the serial resistance of the leads is accounted for by potential drop from the contacts obtained by solving the DD equation. Further, the contact resistance is taken into account by computing the tunneling through the Schottky barrier (also via NEGF method). For the second example, we simulate a two-dimensional III-V MOSFET, featuring wrapped-around leads. The channel part of the transistor is modeled by the NEGF method to capture source-to-drain tunneling leakage, which is critical for short-channel devices scaled to sub-10 nm. The (relatively) long leads, are again assigned to the DD solver to calculate the non-trivial potential drop from the external contacts. We benchmark the simulation results with the experimental measurements and then optimize the device design parameters.

We report simulations of logic transistor operation at supply voltages V dd between 0.08-0.18V. Tunnel FETs (TFETs) can operate at low voltage with low off-currents I off , but on-currents I on are greatly reduced by low tunneling probability. The minimum feasible Vdd is constrained not only by the transistor subthreshold swing (SS) given a target /on//off ratio, but also by the reduction of the drain current as the drain Fermi level approaches the channel conduction-band energy. This output conductance reduces the TFET voltage gain and impairs the logic gate noise margin; increasing the TFET threshold voltage Vh increases the noise margin while reducing both I on and I off . In ballistic simulations with 10 -3 A/m I off , triple-heterojunction tunnel FETs (3HJ-TFETs) show >50% tunneling probability and a high 265A/m I on at V dd = 0.18V and 195A/m at V dd =0.12V. In simulations with an optical deformation constant (proportional to scattering strength) of 220meV/nm, consistent with μ=1.1×10 5 cm 2 V -1 s -1 , reduces I on by 31% given fixed I off and V dd . In ballistic simulations, increasing Vth by 0.02 V above that required for 10 -3 A/m I off , a noise margin of 24% of V dd is obtained at V dd =0. 12 V.

We propose InAs/GaSb ultrathin-body tunneling field-effect transistors (TFETs) using confinement in the (1 ($) over bar0) plane and transport in the [110] direction to increase the tunneling probability by reducing the tunnel barrier energy and hole effective mass. To reduce the OFF-state leakage current, we add an InAs/In1-nAlnAs1-nSbn heterojunction to the channel, which increases the valence band barrier. The heterojunction also increases the tunneling probability and ON-current by reducing the tunneling distance through the p-n junction and introducing a resonant state. A fully atomistic non-equilibrium Green function quantum transport approach in NEMO5 is used to explore the design space. While choosing 10(-3) A/m OFF-current (I-OFF) and a 0.3 V power supply, we simulate 270 A/m ON-current (I-ON) for a 30-nm gate length and 170 A/m for a 15-nm gate length (L-g), while a conventional 15-nm L-g GaSb/InAs TFET under (001) confinement shows only 24 A/m I-ON.

Ideal, completely coherent quantum transport calculations had predicted that superlattice MOSFETs may offer steep subthreshold swing performance below 60mV/dec to around 39mV/dec. However, the high carrier density in the superlattice source suggest that scattering may significantly degrade the ideal device performance. Such effects of electron scattering and decoherence in the contacts of superlattice MOSFETs are examined through a multiscale quantum transport model developed in NEMO5. This model couples NEGF-based quantum ballistic transport in the channel to a quantum mechanical density of states dominated reservoir, which is thermalized through strong scattering with local quasi-Fermi levels determined by drift-diffusion transport. The simulations show that scattering increases the electron transmission in the nominally forbidden minigap therefore degrading the subthreshold swing (S.S.) and the ON/OFF DC current ratio. This degradation varies with both the scattering rate and the length of the scattering dominated regions. Different superlattice MOSFET designs are explored to mitigate the effects of such deleterious scattering. Specifically, shortening the spacer region between the superlattice and the channel from 3.5 nm to 0 nm improves the simulated S.S. from 51mV/dec. to 40mV/dec. I. INTRODUCTION

III-V tunneling field-effect transistors (TFETs) offer great potentials in future low-power electronics application due to their steep subthreshold slope and large on current. Their 3D quantum transport study using non-equilibrium Green's function method is computationally very intensive, in particular when combined with multiband approaches such as the eight-band K.P method. To reduce the numerical cost, an efficient reduced-order method is developed in this article and applied to study homojunction InAs and heterojunction GaSb-InAs nanowire TFETs. Device performances are obtained for various channel widths, channel lengths, crystal orientations, doping densities, source pocket lengths, and strain conditions.

Strain engineering has recently been explored to improve tunnel field-effect transistors (TFETs). Here, we report design and performance of strained ultra-thin-body (UTB) III-V TFETs by quantum transport simulations. It is found that for an InAs UTB confined in [001] orientation, uniaxial compressive strain in [100] or [110] orientation shrinks the band gap meanwhile reduces (increases) transport (transverse) effective masses. Thus it improves the ON state current of both n-type and p-type UTB InAs TFETs without lowering the source density of states. Applying the strain locally in the source region makes further improvements by suppressing the OFF state leakage. For p-type TFETs, the locally strained area can be extended into the channel to form a quantum well, giving rise to even larger ON state current that is comparable to the n-type ones. Therefore strain engineering is a promising option for improving complementary circuits based on UTB III-V TFETs.

We describe the design of double-gate InAs/GaSb tunneling field-effect transistors (TFETs) using GaSb electron wave reflector(s) in the InAs channel. The reflections from the source p-n junction and from the reflector(s) add destructively, causing the net transmission to approach unity at certain energies. The energy range of transmission enhancement can be broadened by the appropriate placement of multiple barriers. With 10-3 A/m OFF-current (IOFF) and a 0.3 V power supply, the subthreshold swing is improved from 14.4 to 4.6 mV/decade and the ON-current (ION) is improved from 35 to 96 A/m, compared with a conventional GaSb/InAs TFET.

With transistors approaching scaling limits, demonstrating a record device demands ∼20–40 process steps, many at extreme resolution. Facing this, how might a Ph.D. student steer the future of VLSI or of wireless systems? Beyond exploring yet more new channel materials, whether 2D or 3D, we explore below other options.

We report design of double-gate metal-oxide-semiconductor field-effect-transistors having InGaAs/InAlAs superlattices between the N+ source and a planar InGaAs channel. As with nanowire superlattice transistors, the 2-D superlattice bandgap reduces injection into the channel of electrons having energy above the source Fermi energy. Simulated ballistic transport characteristics of FETs using a three-well superlattice show 29-37.5-mV/decade minimum subthreshold swing and 390-A/m ON-current given 0.1-A/m OFF-current and a 0.2 V power supply.