Electrical erase of hole-scarce IGZO FeFETs so far relies on fringing field by aggressive channel length scaling, which is difficult to reconcile with $\mu \mathrm{m}$-long channel in 3D vertically stacked cells. In this study, we report on IGZO FeFETs with a Dual-Gate (DG) architecture that enables stable $\mu \mathrm{s}$-erase over channel lengths from $0.1 \mu ~\mathrm{m}$ to $10 \mu ~\mathrm{m}$, together with 1e8-cycling endurance. Moreover, for the first time, we demonstrate 3D vertically stacked DG IGZO FeFET strings with 5 word lines, showing robust ferroelectric memory window. The fabricated 3D DG devices achieve fast program $(100 ~\text{ns})$ and erase $(10 \mu ~\mathrm{s})$, providing a low-voltage and highendurance alternative to NAND flash for data staging/offloading-oriented HBS in AI inference.

Despite the historical growth of storage technologies, such as 3D NAND flash, hard disk drives, and tape storage, each of them is facing inherent scaling limitations. 3D NAND flash suffers from rising costs due to the complex 3D fabrication process. The growth rate of the areal bit density for hard disk drives is limited due to superparamagnetic behavior. Tape storage, though, continues to scale in areal bit density, has the disadvantage of high latency. To address these challenges, an alternative memory, “colloidal memory,” is suggested. This memory concept consists of an array of access devices and nanocapillaries immersed in a colloidal mixture of two particle types, which are encoded as “0” and “1”. Using dielectrophoresis, particles are written in the nanocapillaries, where the order of these particles represents a bit string. In this paper, we showed that the theoretical areal bit density is up to approximately 160 Gbit/mm2. The design criteria for two particle types, protagonistic and antagonistic particles, are established through both a conventional core-shell model and an advanced electrokinetic model. Then, the writing and reading operations are investigated to evaluate the performance characteristics. This allows us to estimate the potential application space for the colloidal memory. Ultimately, this work introduces the colloidal memory as a novel memory concept and assesses its feasibility.

As logic scaling enters the angstrom era, vertically stacked complementary field-effect transistors (CFETs) based on atomically thin two-dimensional (2D) semiconductors offer a potential route to extend device scaling beyond the A2 node. Here, we develop an A2-oriented 2D CFET integration flow with a CPP of 36 nm and Lg of 10 nm and present initial demonstrations of several key process modules. Despite their atomically thin channels, 2D GAA CFETs do not provide a contacted poly pitch scaling advantage over Si GAA CFETs at the A2 node, because contact formation constraints impose a similar minimum CPP of 36 nm. We also combine a critical assessment with a multiscale power-performance-area (PPA) evaluation framework spanning quantum transport simulations, compact-model generation, A2-targeted 2D CFET gate-all-around (GAA) integration-flow definition, parasitic extraction and circuit-level benchmarking. Our analysis, however, shows that the expected benefits of 2D GAA CFETs are strongly constrained by non-idealities, in particular high contact resistance and dominant layout-induced parasitic capacitances. Although architectural optimization can improve the Ieff/Ceff ratio, the associated rise in absolute capacitance limits circuit-level gains. Meaningful progress will require co-optimization of contacts, transport and parasitics, together with 2D-specific CFET architectures.

Understanding the interfaces between a contact metal and a two-dimensional (2D) semiconductor, as well as the dielectric gate stack and the same 2D material in transition metal dichalcogenide (TMD) based transistors, is a crucial step towards the introduction of TMD materials into advanced logic nodes. In particular, for the contact metal/2D interface, one of the key parameters is the Schottky barrier height (SBH), which is frequently extracted based on temperature-dependent subthreshold characteristics of TMD field-effect transistors (FETs). However, recently, using this methodology has resulted in rather low extracted SBH values for TMD-based transistors, which seems inconsistent with the low on-current levels in said devices. Here, we therefore connect measured device characteristics on monolayer (ML) MoS2 transistors with technology computer-aided design (TCAD) simulations. In particular, our analysis shows that low SBHs can be incorrectly extracted when the interface trap density Dit is substantial and exhibits, at the same time, a significant temperature dependence, as is the case for TMDs. In fact, TCAD simulations and comparison with the obtained electrical data reveal that the actual SBH is substantially larger than what is extracted when ignoring the above mentioned details of Dit.

Airgaps have been proposed to mitigate interwordline interference in vertically scaled 3-D NAND flash memories. Here, we show with calibrated simulations that specific airgap configurations also improve the memory operation by increasing the electric field around carrier injection points. We investigate both cylindrical gate-all-around and vertical trench cell architectures. For gate-all-around cells, we find a significant reduction of the programming voltage and improvement in erase onset when the airgaps extend into the tunnel oxide. For trench cells, we propose an inter-channel airgap configuration that strongly improves the programming operation, making it competitive with the gate-all-around architecture.

Despite charge trap flash memories being commercialized, the detailed understanding of the underlying physics remains limited. Here, we therefore evaluate common assumptions for the in- and ejection of charge carriers in the trapping layer, by comparing to measurements of both standard SONOS and engineered SONONOS devices. We find a strong impact of these assumptions on the peak of the trapped charge profile as well as on the accumulation near the blocking oxide. Finally, we highlight the need for a non-local detrapping model.

We investigate electron transport in multilayer 2H-transition metal dichalcogenides (2H-TMDs), using WS2 as a representative material due to its prototypical band and phonon structure shared across the 2H-TMD family. Employing first-principles calculations, we incorporate full-band electronic structures and electron–phonon matrix elements within the Boltzmann transport equation framework to study both low-field mobility and high-field velocity characteristics in monolayer (ML), bilayer (BL), and trilayer (TL) WS2. A key focus of this work is the role of multivalley dynamics, particularly the influence of K–Q valley separation (EKQ) on transport behavior. We show that mobility is highly sensitive to EKQ, with larger separations favoring K valley occupation and enhancing mobility due to reduced intervalley scattering and lower effective mass. As the number of layers increases, EKQ decreases, leading to mobility degradation, although TL exhibits partial recovery due to contributions from additional subbands. We further demonstrate that valley engineering—e.g., tuning EKQ via lattice modification—can significantly improve mobility. At high carrier concentrations and high fields, however, both valleys are populated regardless of separation, resulting in reduced mobility and saturation velocity. These findings provide critical insights into the design of high-performance electronic devices based on layered TMDs.

CFETs based on 2D materials hold the potential to replace Si as a channel at advanced technology nodes. In this work, gate-all-around (GAA) nanosheet FETs with the monolayer MoS2 channels are presented. The MoS2 monolayer was successfully suspended above the oxide trench of varying lengths. Less than 20% sag was observed up to a trench length of 200 nm. For the first time, a gate-first process, in combination with critical point drying, is introduced to scale down GAA nanosheet FETs to 50 nm channel width and length without introducing damage to the monolayer MoS2. Perfect conformal gate stack deposition on the monolayer MoS2 sheets is achieved by using TMA 'soaking' treatment. The successful demonstration of monolayer GAA 2D nanosheet FET further shows high potential as a basic component for the future 2D CFET chips integration.

In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position. Once the trap energy distribution is extracted, it is used as input in transient TCAD simulations to reproduce the experimental hysteretic transfer characteristics. Our method is widely applicable to any 2D channel/gate stack combination. Here, it is demonstrated on FAB-integrated devices with AlOx/HfO2 gate oxide. A Gaussian-approximated defect band in the AlOx interlayer centered at a position of about 0.1 eV below the conduction band minimum of WS2 is obtained. Based on this energy position, it is concluded that aluminum interstitial and oxygen vacancies are the defects giving rise to the observed hysteresis. These defects are detrimental to the stability of the studied devices as they are easily accessible by channel carriers during on-state operation. A prominent hysteresis obtained during measurements is consistent with this conclusion.

The performance of 2D material-based field-effect transistors (2D FETs) is significantly influenced by the vertical extension, or depth, of electrostatically doped side Schottky contacts, which is determined through etching. This study employs TCAD modeling to compare back-gated FETs with varying source/drain contact depths and channel lengths. Results indicate that deeper side contacts hinder electric field crowding at the metal/channel interface, resulting in wider Schottky barriers, diminished carrier tunneling, and reduced on-state current. In contrast, introducing a low-k dielectric beneath the source and drain yields the opposite effect. Therefore, in the development of industry-compatible 2D FETs, the depth and design of side contacts must be carefully optimized, as they are critical factors in achieving low-contact resistance devices.

We propose a Monte Carlo framework including (de)trapping to describe the non-equilibrium operation of charge trap flash memories. We thereby base the empirical carrier distribution that was proposed in recent studies on physical parameters. After an outline of the simulation procedure, we show how carrier trapping and detrapping is included. Finally, we illustrate the simulators' capabilities via simulations of the programming and retention operations, highlighting the insight into the carrier dynamics that this approach enables.

In this work, stacked nanosheet FETs with monolayer MoS2 channels are presented. At a channel length of 40 nm, the transistor exhibits a remarkable $\mathrm{I}_{\text{ON}}-451\ \mu \mathrm{A}/\mu \mathrm{m}$ at $\mathrm{V}_{\text{DS}}=1\ \mathrm{V}$, achieved with two tiers of monolayer-MoS2 channels. The device has a record $\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}} > 10^{9}$ and a yield of 96.59%, which shows good electro-static control in the nanosheet channels. We compare these results to dual gate 2D FETs and show how learnings on the planar devices can be utilized in a gate-all-around case. The successful demonstration of stacked 2D nanosheet FETs with high performance further extends Moore's Law scaling with the future 2D CFETs application.

Evidence of microscopic inhomogeneities of the side source/drain contacts in 300 mm wafer integrated MoS2 field-effect transistors is presented. In particular, the presence of a limited number of low Schottky barrier spots through which channel carriers are predominantly injected is demonstrated by the dramatic current changes induced by individual charge traps located near the source contact. Two distinct types of "contact-impacting traps" are identified. Type-1 trap is adjacent to the contact interface and exchanges carriers with the metal. Its impact is only observable when the adjacent contact is the reverse-biased FET source and limits the channel current. Type-2 trap is located in the AlOx gate oxide interlayer, near the source contact, and exchanges carriers with the channel. Its capture/emission time constants exhibit both a gate and drain bias dependence due to the high sensitivity of the contact regions to the applied lateral and vertical fields. Unlike typical channel-impacting oxide traps, both types of reported defects affect the Schottky barrier height and width rather than the threshold voltage and result in giant random telegraph noise (RTN). These observations indicate that the contact quality and geometry play a fundamental role in the ultimate scaling of 2D FETs.

Until the early 2000s, two-dimensional (2-D) materials were presumed to be fundamentally unstable; now, they might be the most promising candidates to replace silicon in scaled MOSFET technology [1]. Throughout the scaling roadmap, silicon has been the channel material of choice thanks to its high carrier mobilities, natural ubiquity, good quality native oxide and well-controllable crystallinity. This has remained true with the introduction of the FinFET architecture, which counteracts short-channel effects (SCE) by partially enveloping the channel with the gate. For gate lengths $(L_{\mathsf{G}})$ below 20nm, however, even more disruptive architectures are under investigation in which the channel consists of a stack of wide and thin “nanosheets” surrounded by the gate on all sides (see Fig. 1). In such devices, reducing the thickness of the nanosheets improves gate control and thereby prevents SCE. Unfortunately, the mobility of carriers in silicon degrades significantly below a thickness of 3nm, owing to enhanced scattering due to thickness variations along the length of the channel. The channel mobility is further degraded by dangling bonds at the surfaces, which increase in relative importance as the thickness is scaled. The mobility penalty and associated drive current loss in thin layers of Si therefore poses a fundamental limitation to $L_{\mathsf{G}}$ scaling in Si channel transistors.

Scaling the vertical cell pitch to increase bit density in 3-D NAND flash memories degrades both the cell transistor characteristics and the memory operation. Here, we therefore investigate an inner gate to mitigate the scaling impact in macaroni channel devices. We evaluate several scenarios with varying complexity using calibrated TCAD simulations: from keeping the inner gate voltage grounded to coupling it to the read gate. We find a trade-off between improved cell transfer characteristics and program voltage determined by the inner gate to read gate coupling ratio.

The low quality of gate dielectrics deposited on 2D channels and the resulting poor reliability of 2D FETs are major issues that need to be addressed as a high priority. In this work, we compare 300 mm integrated dual-gate WS2 FETs with two different interlayers (SiO x and AlO x ) in the top HfO 2 -based gate stack by means of hysteresis measurements. The collected data enable the extraction of essential properties of defects in the gate oxide, which are commonly recognized as the main cause of instability of 2D FETs. In particular, the hysteresis width is evaluated as a function of the measurement sweep rate in order to investigate the time constants of the dominant defects in both interlayers. Finally, a new measurement-simulation scheme to extract the energy distribution of defects causing hysteresis is proposed. We observe that defects in AlO x -capped devices have slower capture/emission time constants and much lower energy density approaching the conduction band minimum of the channel than those in SiO x . Therefore, A1O x reduces hysteresis and improves reliability compared to SiO x .

We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.

Flash memory with a charge trap layer (CTL), also known as silicon-oxide-nitride-oxide-silicon (SONOS), is the most common type in production, yet there is a lack of consensus on the physical modeling of its operation. In Part I, we therefore proposed a full TCAD model based on an energy relaxation approach and showed that it captures experimentally observed memory operation. This numerical model, however, comes with considerable complexity and computational cost. In Part II, we therefore construct a semianalytical model based on similar physical assumptions, called Pheido, to be as simple as possible. We first derive the model equations based on a balance of current densities, detailing the approximations made. We then use Pheido to analyze the various regimes of an experimental incremental step pulse programming (ISPP) curve and compare it to the full TCAD model derived in Part I. Finally, we investigate the impact of material and structural cell parameters on the ISPP curve, illustrating how the Pheido model offers wide utility at low computational cost.

The main limitations of the current dynamic random access memory (DRAM) technology are its scalability and power consumption. These constraints can be overcome by using an In–Ga–Zn–oxide (IGZO) transistor that offers a low OFF-current and high scalability. For that, the IGZO device performance needs to be optimized, which includes increasing its ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and ${V}_{\text {TH}}$ . By combining experiments on scaled industry-relevant devices with ab initio calculations, we show that IGZO composition impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and ${V}_{\text {TH}}$ through modifying channel mobility and carrier concentration. In the studied composition range, ${I}_{ \mathrm{\scriptscriptstyle ON}}$ increases with higher In % and lower Ga %, which is opposite to the ${V}_{\text {TH}}$ trend. Scanning the whole IGZO composition space with ab initio calculations, we predict that films with In < 10% and 20% < Ga < 80% might be beneficial for improving ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and ${V}_{\text {TH}}$ .

3D Trench cells with a vertical flat channel have been proposed to increase the cell density over 3D NAND gate-all-around (GAA). In this work, we investigate the device characteristics of Trench cells. In absence of curvature, Trench cells exhibit inferior program and erase in comparison to a GAA reference. However, the memory window of Trench cells is significantly improved with channel width scaling, gate stack engineering and metal gate integration. This study also provides a basis for design and fabrication of future ultradense 3D NAND memories based on the Trench architecture.