We present the smallest 2.16µm pitch voltage domain global shutter pixel built on a single silicon layer. A novel and very compact pixel architecture is used along a very dense front-end capacitor integration. Leading to the smallest sensor size for the given 800x700 resolution. This pixel is associated to a logic circuit through 3D Cu-to-Cu hybrid bonding process providing state-of-the-art on-chip data processing and interface. Good performance trade-off is achieved with high QE and spatial resolution. Noise figures are also remarkable, allowing up to 90dB linear dynamic range in a single frame using spatially split exposure mode.

This paper demonstrates a 3-tier CMOS image sensor combining 3D Sequential Integration (3DSI) for the 2tier pixel realization & Hybrid Bonding (HB) for the logic circuitry connection. The pixel transistors are fabricated sequentially above the photogate through innovative thin SOI device technology offering scalability advantages versus its bulk counterpart. The demonstrated 3DSI pixel with dual carrier collection offers an attractive dynamic range (106dB, Single Exposure) versus pixel pitch $(1,4 \mu \mathrm{m})$ trade-off.

Coupling CEA (CEACAM5) on tumor cells and CD3 on T-cells by CEAxCD3 bispecific antibodies activates the latter to destroy CEA-positive cancer cells. Clinical activity is, however, limited, in part by insufficient T-cell activation, dose-limiting toxicities or immunogenicity. Combination with CEA-targeted CD28-costimulation shall increase activity and, when sequentially given, reduce the risk of cytokine release syndrome. We present here preclinical data for the combination of NILK-2301 ± NILK-3301. Antibodies were generated using LCB's fully human κλ body platform based on a common heavy chain and on one κ and one λ light chain, determining specificity and affinity. Non-CEA-targeted CD28-costimulation and superagonism were excluded using T-cell proliferation and activation assays. T-cell dependent cytotoxicity (TDCC) was assessed using colorectal (3), lung (2), and gastric (2) cancer lines with human peripheral blood mononuclear cells (PBMC) in vitro and with a xenograft NOG/human PMBC model in vivo. NILK-3301 is not superagonistic and activates T-cells only in the presence of CEA-expressing target cells and primary T-cell stimulation. In vitro, NILK-2301 induces dose dependent killing of CEA-positive cell lines. Combination of NILK-2301 (1nM) + NILK-3301 vs. NILK-2301 alone (10nM) induces 3-8-fold increased TDCC including CEA-low expressing lines (e.g., HT-29 [40% vs. 5%] or KATO-III [65% vs. 28%]), increased CD25-expression (CD4+ [75% vs. 5%], CD8+ [85% vs. 40%]), and T-cell proliferation (CD4+ [70% vs. 5%], CD8+ [65% vs. 40%]). Using a two-dose functional assay, sequential vs. simultaneous NILK-2301/NILK-3301 dosing conveys equal activity at reduced IL-6, TNFα, IFNγ, and IL-2 release. In vivo, NILK-2301 (10 mg/kg IV, BIW) decreases tumor progression. Simultaneous or sequential (d+2 or d+4) combo treatment with NILK-3301 induces markedly improved activity and tumor regression in 8/8, 8/8, and 6/8 mice. NILK-2301 is active as single agent. NILK-2301 + NILK-3301 combination treatment significantly increases activity already at low NILK-2301 doses with reduced cytokine release when given sequentially. IND-filing for NILK-2301 is expected in Q4/2022.

We have developed a $1.62\mu \mathrm{m}$ pixel pitch global shutter sensor optimized for imaging in the near infrared (NIR) and shortwave infrared (SWIR) regions of the light spectrum. This breakthrough was made possible through the use of our colloidal Quantum Dot (QD) thin film technology, which we have named Quantum Film (QF). We have scaled up this new platform technology to our 300mm manufacturing toolset. The challenges associated with the introduction of solution-processed, colloidally grown lead sulfide (PbS) QDs in an industrial 300mm fab environment were successfully overcome. The QF photodiodes, leveraging either NIR or SWIR sensitive QDs, were optimized for high quantum efficiency (QE), low dark current and immunity to operating stress. Global shutter pixel arrays, with pixel pitch of $2.2\mu \mathrm{m}$ and $1.62\mu \mathrm{m}$ exhibit unprecedented QE of >50% and MTF @ Nyquist/2 of 0.75 and 0.6, respectively. The robustness of our 300mm Quantum Film technology was fully assessed and reliability in terms of meeting all required lifetime specifications for consumer electronics and other potential applications has been demonstrated.

3D sequential integration (3DSI) is envisioned for highly miniaturized smart imagers and fine pitch logic and memory imbrication. This paper describes partitioning in 3DSI and design methodologies. A status is also done on low temperature processes and device performance adapted for these applications (i.e. digital $\mathrm{V}_{\text{DD}}\leq 1\mathrm{V}$ and analog $\mathrm{V}_{\text{DD}}\geq 2.5\mathrm{V}$ devices).

A new pixel architecture providing HDR capability coupled with excellent low-light performance and compatibility with pulsed light sources or fast moving objects is presented. The pixel concept is based on a combination of electron collection via a pinned diode for low signal levels, and hole collection with capacitive storage for higher signal levels. The accumulated electrons and holes are generated by the same incident photons. We demonstrate this concept with a 3.2μm pixel fabricated in a back-side illuminated (BSI) process including capacitive deep trench isolation (CDTI). Introduction Several methods of implementing high dynamic range (HDR) capabilities in a CMOS image sensor have been developed thus far. In most cases these rely either on additional devices within the pixel, or on multiple successive integration sequences [1,2]. These solutions generally result in degraded low light sensitivity due to poor fill factor, or image artefacts depending on illumination conditions respectively. The pixel presented in this work aims to address both of these weaknesses. Hole collection and storage Electron collection, storage and readout is performed in a similar manner to the standard 4T operations, therefore the focus of this section is the novel hole management functionality. Fig. 1: Pixel schematic With a typical 4T-style pixel, once an electron-hole pair has been generated by an incident photon, the electron is collected but the hole – which is considered to be redundant – is drained through the substrate contact and lost. To permit hole collection, the substrate of each pixel is electrically isolated with respect to the neighboring ones. This isolation is achieved through the use of deep trenches which penetrate the full silicon depth of the BSI sensor and fully surround the photodiode area. Such deep silicon trenches have already been used to prevent electrical crosstalk in BSI sensors [3]. As shown in figure 1, an NMOS transistor (RST_PSUB) is used to reset the pixel substrate to ground at the beginning of the integration or during the readout phase. The HDR performance of this pixel architecture is directly linked to the capability to store holes in quantities greatly exceeding the electron full well capacity. The hole full well is a function of the pixel substrate capacitance (C1): a 73 fF capacitance will store 912 kh+ over a 2V swing. This capacitance value is achieved by utilizing the isolation trenches. These are fabricated with an oxide liner and subsequently filled with polysilicon to form capacitive deep trench isolation (CDTI). Negatively-biased CDTI is known to improve dark current metrics compared to oxide-only isolation trenches [4]. A schematic cross section view of such a pixel is presented in figure 2. Fig. 2: schematic cross section of the pixel Hole read out The hole signal is the voltage reached by the pixel substrate (Vsub). Starting from 0V, and with a potentially large swing, it is not practical to directly measure this with an NMOS transistor, therefore a capacitive-coupling design has been chosen instead. The pixel substrate is connected to the sense node with a dedicated capacitor (C2, Fig. 1). The hole readout design has multiple benefits: firstly, it efficiently reuses the existing pixel circuitry; the only active device added to the pixel is the RST_PSUB transistor. Secondly, it offers ample flexibility of the capacitance ratio C2/Csn (sense node capacitance) to enable the high voltage swing on Vsub to be converted

In recent years, unprecedented DNA sequencing capacity provided by next generation sequencing (NGS) has revolutionized genomic research. Combining the Illumina sequencing platform and a scFv library designed to confine diversity to both CDR3, >1.9 × 10(7) sequences have been generated. This approach allowed for in depth analysis of the library's diversity, provided sequence information on virtually all scFv during selection for binding to two targets and a global view of these enrichment processes. Using the most frequent heavy chain CDR3 sequences, primers were designed to rescue scFv from the third selection round. Identification, based on sequence frequency, retrieved the most potent scFv and valuable candidates that were missed using classical in vitro screening. Thus, by combining NGS with display technologies, laborious and time consuming upfront screening can be by-passed or complemented and valuable insights into the selection process can be obtained to improve library design and understanding of antibody repertoires.

The 1-transistor floating body (1TFB) memory presents a possible solution for embedded memories, as it appears to scale, and does so with standard processing. This study investigates the signal limits of 1TFB memory as technology scales. It shows that although the signal DeltaVth remains nearly constant with scaling, the memory cells become susceptible to disturbance because the amount of stored charge decreases. In addition, the transistor mismatch increases with scaling, thus limiting the ability of conventional sensing methods to correctly read the memory.

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.

In this paper, we report on parasitic bipolar conduction occurring in floating-body effect based capacitor-less DRAMs. A way to include these effects into a previously developed model is presented. The enhanced model is then compared with electrical data realized on triple-well nMOSFET devices within the 26/spl deg/C-100/spl deg/C temperature range.

As capacitor-less DRAM cell appears to be an interesting candidate for future embedded memory generations, we paid particular attention to overall performance and scalability of the 1T-Bulk concept. We have analysed this architecture through our analytical model. Then we have fabricated devices and we have measured the influence of different technological parameters: floating body doping level, gate length and gate oxide thickness. The 1T-Bulk cell is demonstrated to be a promising candidate for eDRAM applications up to the 45nm technological node.

An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 /spl mu/A. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell.

A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85/spl deg/C. Nondestructive reading is demonstrated at 25/spl deg/C and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising double gate architecture.

We report on the modeling and characterization of the memory effect observed on triple-well nMOSFETs. First, the mechanisms of charge injection, localization and retention in the floating p-well of triple-well nMOSFETs are investigated and a new model is proposed. Then several electrical characterization set-ups are discussed. Finally, modeled and measured data are compared at room temperature.

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.