RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text{ON}}\times C_{\text{OFF}}$</tex> of 78 fs with a breakdown voltage of 3.7 V.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has emerged over the past few years as the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology are already exceeding what was feasible using GaAs one, new cellular system such as carrier aggregation require even more stringent performances (linearity, power handling, insertion loss, isolation). To address those new requirements, RF SOI technology has to be improved. In this paper, the performances results of the latest generations of RF SOI switch technologies from STMicroelectronics are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also proposed, paving the way for RF SOI technology able to address 5G RF switches challenges.

This paper looks back to the development of highspeed BiCMOS technologies in STMicroelectronics for the past 15 years and discusses the perspectives for next generations through the CMOS angle. Opportunities and challenges of nanoscale BiCMOS technologies are reviewed and BiCMOS055 results are presented to demonstrate the feasibility at 55 nm node. Perspectives to offer FDSOI BiCMOS technologies at 28 nm or 14 nm nodes are analyzed too.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 μm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz fT and 370 GHz fMAX associated with a CML ring oscillator gate delay τD of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

In this paper, we present a W-Band load pull test bench used to improve a characterization of Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT). High accuracy is obtained in Load-pull measurements at 94 GHz on last-generation SiGe HBTs by extracting the input reflection hot S-parameter (S'11), in order to understand the mechanisms of power behavior in the presence of millimeter-wave excitations. The device under test (0.12×4.9μm2) was characterized under large signal load pull showing attractive performance for power amplifier design. A state-of-the-art power density of 22.26 mW/μm2 has been extracted at 94 GHz.

Stress investigations have been carried out on SiGe HBTs from STMicroelectronics BiCMOS9MW technology. The strain created by the stack of metal connections impacts the base bandgap of the transistors: from the reference to the denser dummies structure, a 9.1 meV bandgap energy variation is pointed out. Dummies structures were embedded for both DC and HF characterizations which showed a 25% increase for the collector current, and a 21% and 12% increase for the transit frequencies fT and fMAX respectively.

This paper summarizes the technological developments carried out in STMicroelectronics to raise the fT / fMAX of SiGe HBTs up to ~ 300 GHz / 400 GHz. The noise and power performance in the W-band of different SiGe HBT generations are compared along with CML ring oscillators and circuit results up to the D band.

The influence of an additional annealing in the base/emitter module fabrication of state-of-the-art DPSA-SEG SiGe:C HBTs is studied in this paper. The objective of this annealing is to reduce the extrinsic base resistance R Bx which in previous studies appeared to limit f MAX of DPSA-SEG SiGe HBTs. TCAD simulations and on-silicon measurements are presented for two different base widths. It is shown that the f MAX increase brought by R BX reduction can be traded for a larger f T . A f T /f MAX frequencies couple reaching 320/390 GHz is demonstrated, associated to a CML ring oscillator gate delay time of 2.2 ps.