This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but are more often made by a backside wafer processing. This proposed flow works in a single pass and is based on a dedicated constraint-satisfaction software. In addition to the standard placement rules, the different types of constraints used for 3D frames are clearly identified: alignment, overlapping, mirroring. The method to generate separate frames is described. Results and performance obtained in production, for frames involving two different manufacturing processes for wafer front and backside, are detailed.

In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.

The continuous CMOS performance improvement enhances the interest of the RF CMOS for millimeter wave application. Hence the extension of DC reliability model in the RF domain is becoming critical. Understanding the MOSFET aging influence on the small signal equivalent circuit is a key concern to integrate the RF reliability simulation at compact model level. In this work, an accurate setup which allows the application of RF stress and the monitoring of DC/RF parameters is detailed. Hot carrier stress is performed on MOSFET and a physical analysis of the small signal equivalent circuit aging is done.

In this paper, the design and use of an in situ tuner (IST) aiming On-Wafer multi-impedance method are presented. The conventional method using Off-Wafer tuner is limited by the frequency range and has high losses between this external tuner and the device under test (DUT). Here, the IST is placed near the DUT to achieve higher |Γ| and to cancel losses between the impedance generator and the device. The architecture of the tuner is based on variable lumped R and C elements fulfilled with cold-field-effect transistor and varactors controlled through biasing and associated to coplanar transmission line for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the four noise (NFmin, Rn, Γopt) parameters of 65-nm metal-oxide-semiconductor field-effect silicon transistors through the use of this in situ multi-impedance method. The 75-110 GHz noise test bench using cold-noise source method and the noise measurement are described showing transistor capabilities at MMW.

Today, measurement of 65nm CMOS [1] and 130nm-based SiGe HBTs [2] technologies demonstrate both fT (current gain cut-off frequency) and fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100nm III–V HEMT. This increase allows new millimeter wave (MMW) applications on silicon. One of the success keys is then the passive integration. In this paper, on-chip coplanar waveguides (CPWs), which have been achieved in STMicroelectronics advanced nanometric RF CMOS High Resistivity (HR) SOI (ρ> 1kΩ·cm) process, and characterized up to 325GHz are reported. Moreover, for the first time passive circuits working @ 325GHz have been achieved on silicon and characterized demonstrating state-of-the-art performances and good agreement with electric simulations.

Today, the performances of CMOS technology with fT around 250GHz and fmax higher than 250GHz demonstrates the capability to integrate Millimeter wave applications from a transistor point of view. A key factor is the integration of passive components. In this paper we present, for the first time, the MMW performances of 32 nm Back End Of Line (BEOL) CMOS technology through the achievement of passive components and scalable models (on-chip microstrip transmission lines with losses less than 1dB/mm up to 60GHz) and MMW functions (hybrid coupler, band pass filter and Wilkinson power divider around 77GHz).

RF reliability is becoming an increasing concern for actual technology platforms. In this context, small signal equivalent circuit degradation under hot carrier stress is investigated. It is shown that some lumped elements such as the conductance, the transconductance, the gate-to-drain capacitance, and series resistances are degraded. The application of corrections based on physical phenomenon explains the major part of the hot carrier impact on the small signal equivalent circuit. Furthermore, the overlap gate-to-drain capacitance degradation is emphasized.

RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus our investigation on high performance passive functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, balun, harmonic filter, diplexer and directional coupler have been achieved in a 130 nm SOI CMOS technology. Measured performances are clearly competitive with most commercially available Integrated Passive Device (IPD) solutions, which paves the way of FEM silicon SOCs.

This paper presents a comparison between a pure mode and build in balanced characterization of inductor. As predicted by linear electronic theory, the true mode matrix is equal to the build in matrix for small signal analyses. Moreover, we have proposed innovative test structure, de-embedding techniques and parameter extraction methodology which take advantage of mixed mode S-parameters in order to determine experimentally the self inductance mutual. From modelling point of view, it opens the door for new compact model in order to be able to check and deal with any unbalance in the simulation.

RF front end module (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus our investigation on high performance passives functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, WLAN and GSM/DCS diplexers have been achieved in a 130 nm SOI CMOS technology. Measured performances (insertion losses ~1dB and isolation greater than 20 dB) are clearly competitive with most commercially available Integrated Device Passive (IPD) solutions.

The present work proposes a simple Pad/Thru de-embedding method for multiport S-parameter measurements of differential varactors. The Pad/Thru method is compared to Open/Short de-embedding and leads to the following strengths: reduction of the wafer area required for dummy structure and reduction of the number of measurements required to characterize and de-embed each devices.

This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz f T /f MAX ) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm 2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.

In this paper, the design and use of an In-Situ Tuner (IST) aiming On-Wafer multi-impedance method are presented. The conventional method using Off-Wafer Tuner is limited by the frequency range and has losses between this external Tuner and the Device Under Test (DUT). Here, IST is placed near the DUT to achieve higher |Γ| and to cancel losses between the impedance generator and the device. The architecture of the Tuner is based on variable lumped R and C elements fulfilled with Cold-FET and varactors controlled through biasing and associated to coplanar transmission line (cpw-TL) for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the 4 noise (NFmin, Rn, Γopt) parameters of a 65nm MOSFETs silicon transistor through the use of this in-situ multi-impedance method. The 75–110GHz noise test bench using cold-noise source method and the noise measurement are described showing Transistor capabilities at MMW.

In this paper, for the first time, silicon integrated tuner is presented aiming silicon transistor (HBT, MOSFET) millimeter wave (MMW) noise parameters (NF min , Rn, Gammaopt) extraction through multi-impedance method. This tuner is directly integrated in on-wafer tested transistor test structure. Design, electrical simulation and MMW measurement of the Tuner are described showing capability from 60 GHz up to 110 GHz for CMOS and BiCMOS sub 65 nm technologies characterization. |Gamma| of 0.88 have been achieved at the DUT input in the considered frequency range and tuner insertion losses are less than 20 dB.

In this paper, for the first time, Silicon integrated tuner is presented aiming silicon transistor (HBT, MOSFET) millimeter wave (MMW) noise parameters (NFmin, Rn, Gammaopt) extraction through multi-impedance method. This Tuner is directly integrated in On-wafer tested transistor test structure. The achieved proximity between device under test (DUT) and the developed Tuner allows better impedances (higher |Gammaopt|) for frequency above 60 GHz due to losses reduction between tuner and transistor compared to classical setup using off-wafer impedance generator. The tuner design is based on variable R, C elements fulfilled with cold-FET and varactors controlled through biasing and associated to transmission lines (TL) for phase shifting. Design, electrical simulation and MMW measurement of the Tuner are described showing capability from 60 GHz up to 110 GHz for CMOS and BiCMOS sub 65 nm technologies characterization. |Gamma| of 0.88 have been achieved at the DUT input in the considered frequency range and Tuner losses are less than 20 dB.

During past years, High Resistivity (HR) SOI CMOS technology has emerged as a promising one for the integration of RF applications, mainly because of the improvement of passive component related to HR substrate. This paper summarizes, for the first time, an in depth analysis of different optimization scheme suitable for on-chip inductors fabricated on HR substrate, using advanced 65 nm SOI CMOS technology with 6 copper metal levels. Measurement results demonstrated that proposed optimized SOI inductor architectures, integrated in a standard advanced digital back-end of line (BEOL), could address high quality factor (single ended quality factor greater than 20), have high current capability (up to 260 mA @ 125degC) or could enable a huge area saving (up to 50 %).

SOI technology is now emerging as a promising one for the integration of RF front-end modules, mainly for antenna switches and power amplifiers (PAs). This paper reviews the performances of STMicroelectronics 0.13 mu m High Resistivity (HR) SOI CMOS technology and discusses the potentiallity for SOI technology to capture RF front-end business in the near future.

This paper presents a complete 0.13 mum SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2fF/mum2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors.