We report a novel self-consistent low frequency MOS-CV characterization method for MOS structures on high resistivity substrates, which are typically used for integrated optical and ionizing radiation sensor applications. High frequency (HF) MOS-CV measurements cannot be applied to MOS samples with a large serial resistance due to the low quality factor of the measured small signal impedance. The low frequency (LF) MOS-CV-technique reported here is based on the measurement of the gate current and the change of the gate charge in response to a step-ramp gate voltage signal. In depletion operation mode the applied gate voltage signal drives the MOS structure in a non-steady non-equilibrium what enables a short measurement time. For extraction of the generation current the doping need not be known. The method proposed does not rely on the assumption of a homogeneously doped silicon substrate. It enables a rapid self-consistent determination of the generation current depth characteristic using commercially available measurement equipment.

We demonstrate the increase of available collector emitter voltage of integrated vertical bipolar transistors by means of an additional lateral drift region introduced between sub collector and collector contact region. The chosen approach enables the fabrication of high voltage bipolar transistors for RF power applications alternatively to the construction of deep collector wells in vertical direction by an extra epitaxy step or ion implantation with very high energy. The new approach was verified with a modified standard SiGe:C HBT integrated in a high performance BiCMOS process. After introduction of an additional lateral drift region with a length of 1.2 μm BV CE0 of the HBT has increased from 7 V to 18 V.

Addressing applications such as high performance RF power amplifiers and DC/DC converters with high conversion efficiency we demonstrate a cost effective integration of a complementary medium voltage RF LDMOS module in a 0.25 μm base CMOS flow. The integration of the NLDMOS and PLDMOS transistors requires just three additional mask steps. The NLDMOS has an excellent large signal RF performance up to 6 GHz. Key RF performance figures at 1 dB gain compression are 20 dB gain, 35 % power added efficiency and 0.4 W/mm power density. First prototypes of fabricated 12 V DC/DC down converters and 6 GHz power amplifiers verify the excellent DC and RF performance of the devices.

A 0.13 µm SiGe BiCMOS technology for millimeter wave applications is presented. This technology features high-speed HBTs (fT=240 GHz, fmax=330 GHz, BVCEO=1.7 V) along with high-voltage HBTs (fT=50 GHz, fmax=130 GHz, BVCEO=3.7 V) integrated in a dual-gate, triple-well RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators for frequencies above 200 GHz are demonstrated.

A special reference densimeter has been developed for accurate measurements of densities of natural gases and multicomponent gas mixtures at standard conditions of temperature and pressure (T s = 273.15 K and p s = 0.101325 MPa). The densimeter covers the range from 0.7 kg · m−3 to 1.3 kg · m−3; the total measurement uncertainty in density is 0.020 % (95 % level of confidence). The measurement principle used is the two-sinker method, which is based on the Archimedes buoyancy principle. The certified calibration laboratory of E.ON Ruhrgas AG, Germany, uses this densimeter to verify the standard densities of certified calibration gases (binary and multicomponent gas mixtures). Moreover, the densimeter is used to determine the compositions of commercially available binary gas mixtures with a small uncertainty of (0.01–0.03) mol%.

A 0.13 μm SiGe BiCMOS technology for millimeter-wave applications is presented. This technology features high-speed HBTs with peak transit frequencies fT of 240 GHz, maximum oscillation frequencies fmax of 330 GHz, and breakdown voltages BVCEO of 1.7 V along with high-voltage HBTs (fT = 50 GHz,fmax = 130 GHz, BVCEO = 3.7 V) integrated in a dual gate oxide RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators with fundamental-mode oscillation frequencies above 200 GHz are demonstrated.

The integration of RF NLDMOS transistors into a 0.13 μm CMOS process for operating at X-Band (8.5-10.5 GHz) frequencies with over 11 dB gain and 0.25 W/mm power density and 22% power added efficiency at 1 dB output power compression is presented. The self aligned NLDMOS was modularly integrated into IHP's 130 nm SiGeC BiCMOS platform targeting 1 W X-Band power amplifiers for radar and satellite communication applications.

The use of biogas as regenerative energy can be achieved more efficiently by injecting the treated biogas into natural gas grids since the localisation of the biogas CHP (combined heat and power) plant is made independent from the site of the biogas production. Thus, the utilisation of the heat generated in the CHP plant may be optimised. For that reason, the National and European regulations support injection into the natural gas grid. This paper deals with the general metrological issues concerning injection from the specific aspects of measurement technology. The issues discussed include the adjustment of biogas to the characteristics of natural gas (treatment to produce biomethane) and the measurement of biomethane calorific value. Measuring the calorific value of natural gas today is almost always based on the use of process gas chromatographs specifically designed for the analysis of typical natural gases. Natural gas chromatographs are only suitable under minted conditions for use with biomethane due to differences in the composition of natural gas and biomethane. This paper explains the specific issues and solutions for the measurement of the calorific value of biomethane and their implementation in current plants equipped with injection facilities.

We present a novel single-poly-silicon EEPROM cell for embedded memory. The cell is integrated in a 0.13μm RF-CMOS technology without process modifications and is composed of an NMOS transistor and a MOS capacitor on two isolated P-wells sharing a floating poly-silicon layer. A two-polarity voltage of ±6V is applied for writing and erasing using uniform-channel Fowler–Nordheim tunnelling. Operations faster than 1ms, endurance over 10+3 cycles and data retention longer than 10 years are demonstrated.

We demonstrate the integration of a low-cost, high-voltage complementary LDMOS module with BVdss of -71V and 83V for the PLDMOS and the NLDMOS, respectively, into an advanced industrial 0.25 mum SiGe:C BICMOS process. The essential deep N-well for the high voltage PLDMOS is formed by a single 6MeV P implantation step. BVdss*ft of the NLDMOS accomplishes record values > 900 VGHz.

We present a double-polysilicon SiGe:C HBT module showing a CML ring oscillator (RO) gate delay tau of 2.5 ps, and fT/ fmax/BVCEo values of 300 GHz/350 GHz/1.85V. A key new feature of the HBT module is a connection of the extrinsic and intrinsic base regions by lateral epitaxial overgrowth. This facilitates simultaneously a very low base resistance and a reduced base-collector capacitance. In addition, the RF performance is enhanced for devices rotated by 45deg with respect to the standard orientation due to favorable epitaxial growth behavior.

This work reports on a 130 nm BiCMOS technology with high-speed SiGe:C HBTs featuring a transit frequency of 255 GHz and a maximum oscillation frequency of 315 GHz at an emitter area of 0.17 x 0.53 mum 2 . A minimum gate delay of 3.0 ps was achieved for CML ring oscillators. Breakdown voltages of the HBTs are measured to be BV CEO =1.8 V, BV CBO =5.6 V, andBV EBO =1.9 V.

The authors demonstrate a low-cost, high-performance, high-voltage complementary SiGe:C BiCMOS process. This technology offers three npn SiGe:C devices with fT/BVCEO values of 40GHz/5V, 63GHz/3.5V, and 120GHz/2.1V together with a 32GHz fT/35GHz f max/ 4.4V pnp SiGe:C HBT by adding only three bipolar masks to the underlying RF-CMOS process. With two additional implant masks, a 150GHz, 2.2V npn HBT and either a 43GHz fT/ 65GHz fmax 4.2V pnp or a 38GHz fT/ 70GHz fmax, 5.8V pnp device can be fabricated additionally (in the npn case) or alternatively (pnp case) to the devices of the 3-mask module

In this paper, we present a modular and reliable complementary RF LDMOS (laterally diffused MOS) architecture fully compatible with a 0.13 mum CMOS platform. We demonstrate BVDS*fT values up to 560 and 210 GHzV, respectively, for N- and PLDMOS transistors. A major advantage of the proposed process flow is that the drift region of N- and PLDMOS transistors can be independently optimized for different BVDSwithout affecting the VT

We present a low-cost, modular BiCMOS process for wireless and mixed-signal applications. A SiGe:C bipolar module, a complementary LDMOS module, and a low-power flash memory were combined with a 0.25/spl mu/m CMOS technology to enable SoC integration. The low-cost approach is demonstrated by the fact that only 29 mask steps are applied in total for the full process flow including all modules, a full suite of passives, and 5 metal layers.

In this paper, we study the performance and reliability of LDMOS (laterally diffused MOS) transistors, developed in a 0.25/spl mu/m SiGe:C BiCMOS technology, for two different channel doping schemes a) uniform and b) single-sided halo (SH). We show that SH LDMOS transistors are more reliable and offer better DC and high frequency performance. We also demonstrate BV/sub DS/ *F/sub t/ values up to 630GHzV with SH LDMOS transistors.

A new scheme for the integration of high-performance HBTs with thin-film SOI CMOS is demonstrated. The thickness incompatibility problem of thin-body SOI CMOS and high-performance SiGe HBTs is solved by forming HBTs on silicon islands in the BOX. Low-resistance collector wells are realized by ion implantation into the SOI substrate. SiGe:C HBTs with f(T)/f(max) values of 220 GHz/230 GHz and a BVCEO of 2.0 V and fully-depleted CMOS transistors with 90 ran gate length are fabricated on SOI wafers with 30 nm Si thickness.

We demonstrate a BiCMOS process which uses only 22 mask steps to fabricate four types of SiGe:C HBTs, in combination with a triple-well, 2.5V CNIOS core and a full menu of passive elements. Key process feature is a 2-mask HBT module. We show that transistors with peak f(T) values ranging from 30GHz (@ 7V BVCEO) UP to 130GHz (@ 2.1V BVCEO) can be fabricated with this low-cost module. Among the passives are varactors, polysilicon resistors, and a 2fF/mum(2) MIM-capacitor. Five layers of Al are available, including 2mum and 3mum thick upper layers. SOC ability of the process is demonstrated by a 1M-SRAM yield of typically 70%.

This paper presents a process technology for cost-effective integration of low-power flash memories into a 0.25μm, high performance SiGe:C RF-BiCMOS process. Only four additional lithographic steps are used on top of the baseline BiCMOS process, leading to in total 23 mask levels for the BiCMOS/embedded flash process. Uniform-channel Fowler–Nordheim programmable and erasable stacked-gate cells, suitable for medium density (∼Mbit) memories, are demonstrated. Peripheral high-voltage transistors, with >10V breakdown voltage, are integrated without additional mask steps on top of the flash cell integration. The flash memory integration is modular and has negligible impact on the original CMOS and HBT device parameters.