We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm(2) mg(-1) was obtained.

Mixed signal on-chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with sufficient ruggedness against ionizing radiation and single event burnout. We report on a novel hardening by design approach for radiation tolerant integrated RF NLDMOS transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease TID induced leakage currents the shallow trench isolation (STI) of MOS transistors was replaced by narrow junction isolated regions. For a significant increase of the SEB onset voltage a cascode arrangement consisting of an isolated NMOS and NLDMOS was chosen. The floating NMOS-drain/NLDMOS-source node in the cascode arrangement is always reverse biased which efficiently avoids a turn-on of the parasitic npn bipolar transistor. The rad-hard isolated NMOS/NLDMOS cascode features a breakdown voltage BVDS > 50 V, a maximum cut off frequency fT = 5 GHz and a maximum oscillation frequency fMAX = 14 GHz. In comparison with standard NLDMOS transistors the isolated NMOS/NLDMOS cascode device shows an increase of the SEB onset voltage from 14V to 30V at a linear energy transfer LET of 67.7 MeVcm2/mg and a negligible increase of source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.

To demonstrate a fully integrated RF-MEMS based system including HV generation and switching circuitry, a V-Band (40 - 75 GHz) single-stub impedance tuner comprising four RF-MEMS switches, a 40V charge pump, and LDMOS based HV switches is developed in a 0.25 μm SiGe-BiCMOS technology. The chip size of the designed impedance tuning circuit enables the integration into an on-wafer RF-probe used for noise parameter and load-pull measurements. With the integrated high-voltage generation and switching circuitry the wiring effort, which is necessary to control the integrated RF-MEMS based impedance tuning chip, can be drastically reduced. The operation of the on-chip high-voltage generation and switching circuitry is demonstrated by the measured S-parameters for various combinations of activated RF-MEMS switches. The four integrated RFMEMS switches enable 16 impedance states in the frequency range between 40 GHz and 60 GHz.

In this work, two high voltage LDMOS inverters, a charge pump and a differential ring oscillator are designed and combined with a Ka-band RF-MEMS SPDT (single-pole double-throw) switch in a single BiCMOS chip. The circuit is fabricated in a triple well 0.25 μm SiGe:C BiCMOS process which includes a LDMOS- and a RF-MEMS module. The measured rise and fall times of the high voltage inverter are below 2.5 μs and 2 μs considering a 65 pF capacitor in parallel with a 1 MO resistor as the load caused by the measurement setup. Simulations based on the RF-MEMS electrode capacitance of ∼200fF — as the real case application — result in a drastically decreased rise (charge) time and fall (discharge) time of 10 ns and 8 ns, respectively. The maximum operating voltage of the LDMOS inverter is 45 V, which enables the actuation of the RF-MEMS switch. The measured S-parameters of the RF-MEMS SPDT switch, driven by the developed LDMOS inverters and charge pump, demonstrate the successful implementation.

In order to improve the total ionizing dose (TID) and single event upset (SEU) radiation tolerance of bulk CMOS technologies we applied two constructive measures. TID induced source-drain leakage is suppressed by a junction isolation (JI) of the source drain regions using silicide blocked well regions. To decrease the susceptibility against SEU we introduced a redundancy on transistor level, where each MOS transistor is replaced by a stack of two spatially separated single transistors which share a common gate (CG). The radiation hardness and device performance of the novel JICG MOS transistors fabricated in IHP's 250 nm SGB25RH technology were evaluated.

Mixed signal on chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with a sufficient ruggedness against ionizing radiation and single event burn out effects. We report on the effectiveness of a novel hardening by design approach for radiation tolerant integrated RF power MOSFET transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease the TID related leakage currents the lateral shallow trench isolation (STI) was replaced by narrow junction isolation regions. To significantly increase the onset voltage for SEB events of LDMOS transistors a MOS/LDMOS cascode arrangement has proven as a suitable approach. The common floating MOS drain/LDMOS source node of the cascode arrangement is permanently reverse biased, so that the turning on of the LDMOS parasitic bipolar transistor is suppressed. The properties of the Junction Isolated Cascode LDMOS with respect to area consumption, DC and RF performance and ruggedness against malfunctions due to TID and SEB effects were verified by comparison with standard trench isolated NLDMOS and junction isolated NLDMOS devices. The junction isolated NMOS/NLDMOS Cascode features a break down voltage BVDS > 40V a maximum cut off frequency f T =15 GHz and a maximum oscillation frequency f MAX = 25 GHz. In comparison with standard NLDMOS the laterally junction isolated NMOS/NLDMOS Cascode device shows an increase of the SEB onset voltage from 14V to 24V at a linear energy transfer LET of 67.7 MeVcm 2 /mg and negligible source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.

We demonstrate the modular integration of a high-voltage SiGe:C HBT with 50V BVCEO into a low cost industrial 0.25 μm SiGe:C BICMOS process. The chosen approach of a lateral drift region is very similar to the construction principles applied to the construction of integrated high voltage LDMOS transistors. The construction of a lateral drift region avoids deep collector wells formed by ion implantation with very high implantation energy or epitaxial layer growth. In the chosen approach the emitter and base construction of the standard SiGe:C HBTs, available in the underlying BiCMOS process, remains unchanged. The BVCEO*ft product of the new device reaches values of 200 VGHz.

We report a novel self-consistent low frequency MOS-CV characterization method for MOS structures on high resistivity substrates, which are typically used for integrated optical and ionizing radiation sensor applications. High frequency (HF) MOS-CV measurements cannot be applied to MOS samples with a large serial resistance due to the low quality factor of the measured small signal impedance. The low frequency (LF) MOS-CV-technique reported here is based on the measurement of the gate current and the change of the gate charge in response to a step-ramp gate voltage signal. In depletion operation mode the applied gate voltage signal drives the MOS structure in a non-steady non-equilibrium what enables a short measurement time. For extraction of the generation current the doping need not be known. The method proposed does not rely on the assumption of a homogeneously doped silicon substrate. It enables a rapid self-consistent determination of the generation current depth characteristic using commercially available measurement equipment.

We demonstrate the increase of available collector emitter voltage of integrated vertical bipolar transistors by means of an additional lateral drift region introduced between sub collector and collector contact region. The chosen approach enables the fabrication of high voltage bipolar transistors for RF power applications alternatively to the construction of deep collector wells in vertical direction by an extra epitaxy step or ion implantation with very high energy. The new approach was verified with a modified standard SiGe:C HBT integrated in a high performance BiCMOS process. After introduction of an additional lateral drift region with a length of 1.2 μm BV CE0 of the HBT has increased from 7 V to 18 V.

Addressing applications such as high performance RF power amplifiers and DC/DC converters with high conversion efficiency we demonstrate a cost effective integration of a complementary medium voltage RF LDMOS module in a 0.25 μm base CMOS flow. The integration of the NLDMOS and PLDMOS transistors requires just three additional mask steps. The NLDMOS has an excellent large signal RF performance up to 6 GHz. Key RF performance figures at 1 dB gain compression are 20 dB gain, 35 % power added efficiency and 0.4 W/mm power density. First prototypes of fabricated 12 V DC/DC down converters and 6 GHz power amplifiers verify the excellent DC and RF performance of the devices.

In recent years, several radiation tests on IHP's 0.25 μm SiGe BiCMOS technology SGB25V have been performed. For evaluation by the European Space Components Coordination (ESCC), it has been decided to spin off a dedicated radiation-hard technology SGB25RH for applications in space and high energy physics. In this technology special radiation hard layouts and IP blocks are developed. Because SGB25V and SGB25RH use the same fabrication process, results from investigations on SGB25V are also valid for SGB25RH as long as standard devies are used. All devices under test showed acceptable performance up to radiation levels around 100 kGy (10Mrad). Also, the technology proved to be latch-up-free up to an effective linear energy transfer (LET) of 85MeVcm2 mg-1. For circuit design for radition hard applications a dedicated design kit with new device layouts and special design rules is presented. Additionally, we will sketch future work of modeling and additional devices designed specifically for radiation environments.

A cascode amplifier stage with an isolated NLDMOS and SiGe:C HBT was demonstrated. The main advantages of that circuitry concept are a reduced capacitive portion of the input impedance and a significantly increased power gain in comparison to a single NLDMOS amplifier stage. Additionally a more stable input impedance for different RF input power levels can be obtained. The stable and less capacitive input impedance simplifies the design of integrated impedance matching networks. In a first feasibility study a circuit with a NLDMOS gate width of 90 μm showed a maximum gain of 18 dB and a maximum output power of 10 dBm at 11 GHz. To the authors knowledge the circuit concept of a cascode amplifier containing a HBT and an isolated NLDMOS is presented for the first time.

Isolated LDMOS transistors with thin gate oxides and good RF performance are key components in integrated RF circuits where large voltage shifts are required for the circuit functionality. We demonstrate the modular integration of isolated NLDMOS and PLDMOS focusing on maximal RF performance into an advanced industrial 0.25 μm SiGe:C BICMOS process. A boundary condition for device construction was a limit for maximum deep n-well implantation energy of 750keV. The achieved values BVDSS/fT/fMAX of -21V/10GHz/35GHz for the PLDMOS and 16V/30GHz/53GHz for the isolated NLDMOS, respectively, reflect the excellent RF performance obtained.

The integration of RF NLDMOS transistors into a 0.13 μm CMOS process for operating at X-Band (8.5-10.5 GHz) frequencies with over 11 dB gain and 0.25 W/mm power density and 22% power added efficiency at 1 dB output power compression is presented. The self aligned NLDMOS was modularly integrated into IHP's 130 nm SiGeC BiCMOS platform targeting 1 W X-Band power amplifiers for radar and satellite communication applications.

A new cost-effective concept for RF-LDMOS transistors in a standard 0.13 mu m CMOS technology without process modifications is demonstrated. For the integration of the devices only standard implants of the RF-CMOS process are used. The devices have gate length of 0.35 mu m and share the 7nm gate oxide of the 3.3 V CMOS I/O devices. A breakdown voltage of 19 V and f(T)/f(MAX) values of 25GHz/55GHz, respectively are obtained.

In this paper, we study the influence of the doping profile in the drift region on performance and reliability of RF-NLDMOS transistors in a 0.13 mum SiGe-BiCMOS technology. Two different drift region designs were investigated by simulation and experiment. We show that the design with a shallow compensation implant delivers a significantly improved HCI robustness at a similar level of RF and DC performance. The presented modular integration concept offers NLDMOS devices with breakdown-voltages BVDSS=21 V and peak cut-off frequencies fT=23 GHz. The maximum operating voltage for less than 10% degradation of the on-resistance in ten years is 11 V.

We demonstrate the integration of a low-cost, high-voltage complementary LDMOS module with BVdss of -71V and 83V for the PLDMOS and the NLDMOS, respectively, into an advanced industrial 0.25 mum SiGe:C BICMOS process. The essential deep N-well for the high voltage PLDMOS is formed by a single 6MeV P implantation step. BVdss*ft of the NLDMOS accomplishes record values > 900 VGHz.

HfO2 films were grown by atomic vapour deposition (AVD) on SiO2/Si (100) substrates. The positive shift of the flat band voltage of the HfO2 based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5×1012cm−2. The interface trap charge density of HfO2/SiO2 stacks can be reduced to 3×1011eV−1cm−2 near mid gap, by forming gas annealing. The extracted work function of 4.7eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO2/SiO2 gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO2 based PMOS transistors is 56cm2/Vs.