Internet of Things regroups numerous applications. Among those, a common critical point is definitely power, as well as energy efficiency. 28nm UTBB FDSOI (28FDSOI) has demonstrated its superiority in terms of energy efficiency through numerous publications. This paper demonstrates the extra mile 28FDSOI is able to offer to designers, enabling on one hand ultra-low power (ULP) system-on-chips for wearable and self-sustainable markets, as well as for medium performance and ultra-low power microprocessor units needed for data concentrators.

Wide-voltage-range-operation DSPs bring more versatility to achieve high energy efficiency in mobile applications to increase signal processing complexity and handle a large range of performance specifications. This paper describes a 32b DSP fabricated in 28nm UTBB FDSOI technology [1]. Body-bias-voltage (VBB) scaling from 0V up to ±2V (Pwell/Nwell) decreases the DSP core VDDMIN to 397mV and increases clock frequency by +400% at 500mV and +114% at 1.3V. In addition to technology gains, dedicated design features are included to increase frequency over the full VDD range, considering parameter variations. As depicted in Fig. 27.1.1, the 32b datapath VLIW DSP is organized around a MAC dedicated to complex arithmetic and two dedicated operators: a cordic/divider and a compare/select. Data enters the circuit through a serial interface and code is run from a 64×32b register file. It has been shown in [1] that a given operating frequency can be achieved at a lower VDD in UTBB FDSOI compared to bulk by applying a forward-body bias. An additional design step is achieved in this work by (1) increasing the frequency at low VDD thanks to a specific selection and design of standard cells with respect to power vs. performance and (2) dynamically tracking the maximum frequency to cope with variations.

This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.

Crossroads have always been challenging: they require a decision; in Egyptian and Greek mythology they were often guarded by two sphinxes trying to cheat the traveler with their riddles. The two sphinxes, the knight and the knave, the lady and the tiger, are just few instances of difficult puzzles that have kept logicians and mathematicians busy for the last 5,000 years. Today, you are walking down Moore's Law road when you come to a crossroads: one road brings you into the land of emerging technologies: 14, 10 and 7 nanometer, FDSOI, FinFET, 3D-IC,... beyond and below; the other road holds you into the land of established technologies: 28, 40, 65, and 90 nanometers, possibly even above, A&M/S, MEMS,... Choosing the right road is critical to lead your project and your company to success, but making the right decision is increasingly difficult, as it encompasses complex technical and economic considerations. However, unlike the mythological traveler, you won't run into the sphinxes but, rather, into some of our industry best experts; unlike the sphinxes, they will strive to provide you with honest advice about the "road conditions", and you are allowed to ask multiple questions to them to figure out which road is the best for you.

UTBB FD-SOI technology has become mainstream within STMicroelectronics, with the objective to serve a wide spectrum of mobile multimedia products. This breakthrough technology brings a significant improvement in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. The symbiosis between process and design is key in this achievement enabling to provide already at 28nm node a real differentiation in terms of flexibility, cost and energy efficiency with respect to any process available on the market.

In the last two decades, Semiconductors have successively enabled disruptive market expansions in the PC, consumer and Mobility markets. Electronics have now become an integral part of consumer lives where new product introductions are cadenced by recurring yearly events (CES, IBC, …). This cadence drives the complete electronics industry to renew product portfolios at the same impressive rate. Microelectronics has been the key driver of this evolution, by tracking Moore's law for more than 30 years [1]. In the next two decades, Semiconductors will enable further discontinuities of high societal and economic value. A major roadblock for our industry to enable these next decades of innovation, is to identify and implement perennial solutions towards the ultimate energy efficiency of consumer products [2]. Several paths are to be considered jointly, and will be briefly discussed in the following paragraphs [3].

The continuation of Moore's law by conventional CMOS scaling is becoming challenging. 3D Packaging with 3D through silicon vias (TSV) interconnects is showing promise for extending scaling using mature silicon technology, providing another path towards the "More than Moore". Two years ago, the big unceasing question was "Why 3D?" Today, as we move forward with the concrete implementation of the technology, the questions are now "When 3D?" and How 3D?" There are quite a few brave souls who have taken this disruptive interconnect technology and are investing in it today to gain benefit from it. However, for many the lingering questions remain " Are we there yet?" " Is it now or the future?"This panel brings together key thought leaders in the area of 3D Packaging with 3D TSV interconnects to tell us how they see 3D IC shaping up in the coming year(s) and the challenges that lie ahead associated with TSV in practical design.

With advanced semiconductor technology nodes, power management has become a global problem. In battery powered applications, this problem is even more critical. This article describes a range of design solutions that STMicroelectronics uses to manage dynamic and static power while meeting its targets for area and performance.

Designing in 45nm allows another doubling in transistor density vs 65nm, both for logic gates and for SRAM cells. However, Lithography implications are such that Design rules have to be augmented with recommended rules and regular design, and verified with full Lithography and CMP simulation. Low-power techniques have to be even more elaborate than in 65nm, to compensate for less natural voltage swing in logic and SRAMs, and more gate leakage. Finally, reliability and ESD models have to be taken into account by design and phenomena such as Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) are part of library and chip design verification suites. It is only with a holistic approach encompassing process, device modeling, reliability, litho, memory designers, IO designers, power switch experts, that the full capabilities of the 45nm node will be unleashed.

Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. "Surgeons" suggest a GDSII-centered approach, potentially invasive, while "family doctors" recommend a more pervasive approach, starting from RTL. As in real life, "surgery" and "medicine" represent two different schools of thought in the DFM/DFY arena. Both involve risks. This panel will examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad cross-section of semiconductor industry. Although there is general agreement among the panelists that both approaches are necessary and that prevention is the best way to proceed, they also acknowledge that the surgery may be unavoidable in such "hazardous" conditions as state-of-the-art technologies. However, as always, "the devil is in the details," and the diverse approaches to DFM presented below should make this panel quite interesting. We are also counting on the feedback from the IC design community to assess if these approaches are sufficient and practical enough to deal with the "health hazards." We are looking forward to an exciting discussion that will challenge our esteemed panelists.

Creating ICs in the nanometer age is a high-stakes race that few companies can afford to compete in - and even fewer can win. Hear how senior technologists from the world's top technology companies are striving to improve their chances of success. Will leakage constraints force power-sensitive applications to stay with older technologies, or will there be a bifurcation to a new process technology? Will ballooning capital equipment expenses delay new capacity or price out design rules for mainstream applications? Will silicon-on-insulator and new device structures like FinFETs force rethinking of design, modeling and simulation methodologies? And which EDA technologies, delivered when, will be critical for victory? These senior technologists, from some of the biggest companies in the high tech industry, will discuss and debate how they think the overall industry will successfully transition to the nanometer age. Specific examples from the technologists' broad exposure to industry trends and competitors will help illustrate their forecasts and predictions

Creating ICs in the nanometer age is a high-stakes race that few companies can afford to compete in - and even fewer can win. Hear how senior technologists from the world's top technology companies are striving to improve their chances of success. Will leakage constraints force power-sensitive applications to stay with older technologies, or will there be a bifurcation to a new process technology? Will ballooning capital equipment expenses delay new capacity or price out design rules for mainstream applications? Will silicon-on-insulator and new device structures like FinFETs force rethinking of design, modeling and simulation methodologies? And which EDA technologies, delivered when, will be critical for victory? These senior technologists, from some of the biggest companies in the high tech industry, will discuss and debate how they think the overall industry will successfully transition to the nanometer age. Specific examples from the technologists' broad exposure to industry trends and competitors will help illustrate their forecasts and predictions.

The author examines the dynamics of system-on-a-chip design and addresses the fundamental question of whether there is a reproducible process for achieving the right design at the right time.

Increasingly, today's system-level chips include heterogeneous computing cores which can be general-purpose, signal or network processors. The function of the chip heavily depends on the software created for these processor cores. Therefore, all the concerns of traditional hardware architects or designers will fall into the responsibility of embedded software developers: real-time constraints, low-power requirements, and how to split a series of tasks into various widely different processors.Just as the processor core is integrated into the chip, software development must be integrated into the chip development flow. The implications in terms of design flow and embedded software development tools will be examined based on some actual SoC examples. The trends in the responsibilities and skills of the hardware and software developers will be analyzed and some general directions will be proposed.