The extended scalability of Twin Flash memory cells down to 32 nm half pitch is demonstrated in a conventional planar cell layout. Starting with 63 nm line space array and doubling the number of word lines, a cell size of 0.0112 μm2 can be achieved. By dividing available space into 43 nm cell width and 20 nm space between adjacent cells the electrical cell characteristics could be maintained the same as in the previous 63 nm generation. It was found that the proposed aggressive shrinking of the cell spacing in word line direction results in a cross talk of 300 mV when both neighboring cells are programmed to the highest MLC level. The charge cross talk in charge trapping memory (CT) cells is reported for the first time and becomes an issue when cell spacing between Twin Flash and other CT cells as e.g. TANOS approaches the 20 nm mark.

This article demonstrates that the scaling of the charge trap layer leads to an increasing charge loss in retention mode. This result is assigned to the fact that the blocking aluminum oxide is the main leakage path. It is further presented that the charge distribution moves towards the top oxide during programming and therefore shortens the distance to the leakage path. For thinner charge trap layers, the traps close to the aluminum oxide interface are already filled at lower DeltaVt resulting in higher retention loss for the same Vt shift.

This publication investigates the program simulation of charge trapping memory devices in detail. Three different aspects of the simulation are highlighted which have a major impact on the program characteristics in trap based memories. The analysis is done by a comparison between measurement and simulation. It is shown that the trap capture cross section, the bottom oxide to storage nitride energy band offset and the tunneling injection point, under modified Fowler-Nordheim tunneling conditions, are of major importance for highly accurate simulations. The results provide deeper insight into the mechanisms dominating the program behavior in charge trapping memory devices.

This article details an anomalous erase behavior in charge trapping memory devices which is visible in a characteristic erase hump in transient erase curves. For an initial period of time a Vt increase is seen when erase condition are applied to virgin cells before the expected erasing takes place for longer erase pulse duration. This is attributed to charges injected from the gate corners to the areas above source and drain. This effect significantly deteriorates the erase performance of charge trapping devices compared to the intrinsic erase behavior which can be measured at large area capacitor structures.

This paper investigates the use of a metal control gate for sub 30 nm NAND flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This isThis paper investigates the use of a metal control gate for sub 30 nm NAND Flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This is very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell. very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell.

The extended scalability of Twin Flash memory cells down to 32nm half pitch is demonstrated in a conventional planar cell layout. Starting with 63nm line space array and doubling the number of word lines, a cell size of 0.0112μm2 can be achieved. By dividing available space into 43nm cell width and 20nm space between adjacent cells the electrical cell characteristics could be maintained the same as in the previous 63nm generation. It was found that the proposed aggressive shrinking of the cell spacing in word line direction results in a cross talk of 300mV when both neighboring cells are programmed to the highest MLC level. The charge cross talk in charge trapping memory (CT) cells is reported for the first time and becomes an issue when cell spacing between Twin Flash and other CT cells as e.g. TANOS approaches the 20nm mark.

Floating gate NAND flash memory arrays with 64 cells per string and high-k inter poly dielectric have been fabricated on a 36 nm ground rule using sub-lithographic patterning techniques (pitch fragmentation). The influence of pitch fragmentation inherent critical dimension variations on the electrical parameters of the memory cells such as string saturation current, initial threshold voltage, and program/erase performance has been investigated in detail.

A 63nm Twin Flash memory cell with a size of 0.0225 mum2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.

A 63nm Twin Flash memory cell with a size of 0.0225μm 2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi 2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.

Floating gate memory cells running into scaling limitations caused by reduced gate coupling and excessive floating gate interference, charge trapping in its two variants multi bit charge trapping and charge trapping NAND is the most promising technology for the mid term. For NOR type applications also phase change RAM could appear as a competitor in a few years, but some considerable development is still down the road. Concepts to challenge NAND type applications are still in the early stage. Therefore charge trapping is expected to be the technology of choice for code storage in the short to mid term and for data storage in the mid term timeframe.