This paper investigates the program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for nand application. To describe the program saturation in IPD stacks containing thick suboxides (ges 4 nm) , a simple model was developed, directly yielding the maximum reachable programmed threshold voltage level for a given FG cell geometry. The presented model agrees very well to program saturation measurements carried out on a 48 nm FG nand technology with an IPD composed of SiO2 and Al2O3. By extending the considerations to an arbitrary IPD, this paper represents the first attempt to quantify the IPD current blocking ability required for future scaled FG memory cells.

This paper investigates the use of a metal control gate for sub 30 nm NAND flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This isThis paper investigates the use of a metal control gate for sub 30 nm NAND Flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This is very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell. very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell.

For the first time a stochastic model of the program operation in NAND flash memories is proposed. The model incorporates intrinsic noise effects on the threshold voltage (Vth) distribution of the memory cells in incremental step pulse programming (ISPP) schemes. An excellent agreement of the model with experimental data at 48 nm ground rule is demonstrated. This model for cell-system interaction (MCSI) directly makes the link between memory transistor properties and memory system characteristics. It enables efficient algorithm development as well as evaluation of device concepts for future technology nodes with regard to the expected memory system performance and reliability.

Floating gate NAND flash memory arrays with 64 cells per string and high-k inter poly dielectric have been fabricated on a 36 nm ground rule using sub-lithographic patterning techniques (pitch fragmentation). The influence of pitch fragmentation inherent critical dimension variations on the electrical parameters of the memory cells such as string saturation current, initial threshold voltage, and program/erase performance has been investigated in detail.

Floating gate memory cells running into scaling limitations caused by reduced gate coupling and excessive floating gate interference, charge trapping in its two variants multi bit charge trapping and charge trapping NAND is the most promising technology for the mid term. For NOR type applications also phase change RAM could appear as a competitor in a few years, but some considerable development is still down the road. Concepts to challenge NAND type applications are still in the early stage. Therefore charge trapping is expected to be the technology of choice for code storage in the short to mid term and for data storage in the mid term timeframe.

This work characterizes long channel trigate transistors with respect to the systematic influence of crystal orientation and body doping on performance issues like mobility and Vth adjustment. A fin orientation of 〈1 0 0〉 is found favourable for n-channel, 〈1 1 0〉 for p-channel transistors. Experiment shows that body doping is suitable to taylor Vth, but low doping levels are preferable to reduce Vth variations. The applicability of these long channel results to short-channel transistors down to 20 nm gate length is demonstrated and good performance is obtained.

The trimming of electron beam features is investigated to explore the limits of this scaling technique for the fabrication of nano-scale devices. The semiconductor industry, in particular, needs features below 50 nm, e.g., for extremely small gates for future technology nodes. In addition, sub-lithographic structures are required for other device concepts, such as the fin-type field effect transistor (FinFET). The trimming of very thin layers of calixarene, an organic resist material, as well as an oxide-like resist (hydrogen-silesquioxane) were investigated and extremely small feature sizes, well below 10 nm, were achieved. Resist structures down to 4 nm in width and silicon features of about 8 nm have been successfully fabricated. Different trimming procedures utilizing plasma resist trimming, etching of Tetraethylorthosilicate (TEOS) hard-masks in hydrofluoric acid (HF) and sacrificial oxidation were compared and, for the first time, a comprehensive study of these techniques applied to sub-10 nm-structuring is presented. In summary, results prove the potential of the trimming procedures investigated here, each of which has specific applications.

Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found

Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A fabrication concept, epi-before-bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Various modes of operations are extensively analyzed and compared to 2D simulations. It is experimentally shown that specific off-current requirements can be fulfilled with conventional poly-Si gates.

High density data flash memories are essentially used in mobile applications. Flash devices have a small form factor, high storage density and low power consumption. For logic applications FinFET type devices are known to have good scalability down to 10nm gate length. This device architecture combined with a trapping layer enables memory cells with feature sizes well below 50nm. To show the scaling potential of SONOS FinFET memories, devices are processed on SOI wafers with fin widths varying from 8nm to 30nm and gate lengths scaled down to 20nm. We discuss three different storage modes of FinFET trapping layer NVM devices: (a) single bit SONOS cell, (b) multilevel SONOS cell and (c) NROM dual bit device. For (a) and (b) program and erase is done with Fowler–Nordheim tunneling and for (c) channel hot electrons are used for programming and hot holes are injected for the erasing of the localized charges. SONOS FinFET memory devices show excellent functionality down to 20nm channel length.

In this paper the limits of trimming techniques are explored. Very thin layers of organic resist material are investigated. Further, extremely small feature sizes down to 8 nm are achieved. Different trimming procedures utilizing resist trimming, HF dip of TEOS hard-mask and sacrificial oxidation are compared.

Charge trapping memory structures with Al2O3 dielectrics as a trapping dielectric are investigated in a metal–Al2O3–oxide–silicon configuration with a metal gate of high work function. The devices show very good write/erase characteristics, endurance, retention and disturb behaviour. At elevated temperature, devices with an Al2O3 trapping layer are found to have better retention properties than devices with a silicon nitride trapping layer.

In this paper we present a novel nanogap device architecture for molecular electronics which is fully CMOS compatible and non-invasive to the contacted self-assembled monolayer. The device exhibits precise control over the electrode spacing. Single cells as well as arrays with electrode distances of 2.5 nm have been realized and characterized in terms of basic functionality and yield. Simulations have revealed scalability for feature sizes down to the ten nanometer regime.

In this article, ultra-thin-film SOI transistors fabricated by locally recessing the channel regions are presented. SOI MOSFETs with ultra-thin channels offer better scaling properties than bulk transistors due to suppressed short channel effects, reduced parasitic capacitance and easy lateral isolation. The objective of this work was to establish a fabrication scheme for the production of fully depleted (FD) SOI transistors with channel thicknesses of 20 nm and below. An SEM based direct write electron beam lithography was used to pattern structures in the sub 100 nm range. Special emphasis was put on the pattern transfer which is accomplished by high-density plasma etching using hard masks and subsequent resist free silicon patterning with a high density HBr/O"2 plasma. This enabled transistor channels as thin as 1 nm to be produced. Together with standard CMOS production processes NMOS and PMOS transistors with gate lengths down to 48 nm have been fabricated and electrically characterized. In this way recessed channel SOI transistors with channel thicknesses below 10 nm and gate lengths smaller than 50 nm have been achieved for the first time.

FinFETs were the most favourable double gate transistor for the future CMOS device demands due to their improved turn off behaviour caused by better electrostatic channel control, suits especially for battery powered hand held applications. The device was fabricated with an Eltran SOI wafers. Its transfer characteristics reveals its suitability for its application in low power applications.

Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm. In this paper, we analyse the impact of different combinations of doping profiles and gate sidewall spacer thicknesses on device performance. For this purpose we have simulated fully depleted SOI-MOSFETs with thin undoped silicon bodies using a coupled device and circuit simulation.

This work reports a detailed study of nanoscale ultra-thin (UT) SOI MOSFETs for low power applications. Partially depleted (PD) and fully depleted (FD) NMOS and PMOS devices with a wide range of gate lengths down to 25 nm and silicon thicknesses of 25 nm and 16 nm have been analysed. Gate oxide thicknesses of 2.5 nm and 1.8 nm have also been compared. We demonstrate off current adjustment by channel implantation whereby, together with work function engineering, a suitable solution for multiple Vt SOI CMOS technology could be provided.

Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L-G = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.