In psychological research, acquiring information about mental excitement or central nervous activity is fundamental for assessment. Such information can be used as a psychological measure in various investigations like the embodiment of technical artifacts, e.g., in terms of tool use or human-machine systems. A promising method is measuring a subject's electrodermal activity (EDA), i.e., acquiring information about skin conductance or resistance. However, most commercially available measurement systems are expensive and/or not mobile. The system presented in this paper uses low-cost components, has a small footprint, and is easy to rebuilt for scientific applications. It measures EDA by applying a constant voltage and achieves reasonable resolution by individually amplifying slow and fast electrodermal effects, i.e., level and response. Based on a design from the literature, the paper explains the functionality, extensions, and implementation of the system. A comparative study with a commercial laboratory system is conducted and discussed: although the presented system offers a lower resolution, the quality of the recorded data is deemed sufficient for psychological studies. (C) 2016 Elsevier Ltd. All rights reserved.

So far, metal oxide semiconductor field-effect transistors (MOSFETs) have been fabricated using either optical lithography or imprint lithography with an alignment step between the different layers. Here, we report on the new process for the fabrication of top gate MOSFETs where the number of fabrication steps is reduced significantly. The 3D topography of a top gate MOSFET using as primary master is inversely replicated into a flexible mold that is subsequently transferred to the imprint resist layer. By reactive ion etching, this self aligned 3D pattern is transferred into the underlying semiconductor stack creating functional transistor structures. Preliminary electrical characterizations demonstrate fully operational transistor functions.

We investigate the impact of AlN buffer layers on metal gate work function (WF) of TiN metal inserted polysilicon stacks on silicon dioxide (SiO2) and high-k gadolinium silicate (GdSiO). Atomic layer deposition (ALD) technique is used to achieve atomic control of the buffer layer thickness. High WF of 5.2 eV suitable for p-MOSFETs are obtained by ALD AlN buffer layers and the principles of dipole based WF tuning can be transferred to GdSiO based high-k stacks. The applicability of the AlN buffer layer technique is demonstrated by integration into p-MOSFETs. Hole mobility is found to be unchanged for devices with AlN compared to reference devices without buffer layer.

Abstract not Available.

The paper presents the results of electrical characterization in the wide temperature range (120-320 K) of the interface and bulk properties of high-k LaLuO3 dielectric deposited by molecular beam deposition (MBD) on silicon substrate. The energy distribution of interface state density is presented and typical maxima of 1.2×1011 and 2.5×10 11 eV-1 cm-2 were found at about 0.25-0.3 eV from the silicon valence band. The charge carrier transport through the dielectric at the forward bias was found to occur via Poole-Frenkel mechanism, while variable range hopping conduction (Mott's law) controls the current at the reverse bias.

In this work, epitaxial grown gadolinium oxide (Gd2O3) has been investigated as promising high-k gate dielectric for future CMOS generations. Fully functional metal gate MOS capacitors and MOS field effect transistors (MOSFETs) on p- and n-type silicon substrates with titanium nitride (TiN) gate electrode have been fabricated in a gentle gate-last process and are electrically characterized in detail.

A FUSI NiSi metal gate technology is used to investigate the scaling potential of high-k epitaxial gadolinium oxide (Gd2O3) down to 0.6 nm equivalent oxide thickness. Thermally stable gate stacks have been realized by TiN electrodes on gadolinium silicate. Work function tuning of mid gap electrodes is achieved by insertion of ultrathin AlN buffer layers. Initial results based on sputtered buffer layers are transferred to atomic layer deposition technique in order to achieve atomic control of the thicknesses in combination with conformal deposition.

In this work we present a gate-first process platform for device integration of gadolinium (Gd) based high-k dielectrics and metal gate electrodes. Epitaxial Gd2O3 and GdSiO high-k layers have been integrated with titanium nitride (TiN) gates. Thermal stability of the gate stacks is investigated in detail. Especially the metal inserted polysilicon approach using TiN enables high temperature processing.

We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd"2O"3) from a silicon oxide (SiO"2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).

In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem. Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.

Using scanning tunneling microscopy in an ultrahigh vacuum and atomic force microscopy, we investigate the corrugation of graphene flakes deposited by exfoliation on a Si/SiO2 (300 nm) surface. While the corrugation on SiO2 is long range with a correlation length of about 25 nm, some of the graphene monolayers exhibit an additional corrugation with a preferential wavelength of about 15 nm. A detailed analysis shows that the long-range corrugation of the substrate is also visible on graphene, but with a reduced amplitude, leading to the conclusion that the graphene is partly freely suspended between hills of the substrate. Thus, the intrinsic rippling observed previously on artificially suspended graphene can exist as well, if graphene is deposited on SiO2.

In this abstract, the impact of series resistance on mobility extraction in conventional and recessed-gate ultra thin body (UTB) n-MOSFETs is investigated. High series resistance leads to an overestimation of the internal source/drain voltage and influences the measurement of the gate to channel capacitance. A specific MOSFET design that includes additional channel contacts and recessed gate technology are used to successfully extract mobility down to 0.9 nm silicon film thickness (4 atomic layers). Quantum mechanical effects are found to shift the threshold voltage and degrade mobility at these extreme scaling limits.

In this work we describe the gate first integration of gadolinium silicate (GdSiO) high-k dielectrics and metal gate electrodes into SOI n-MOSFETs. Fully functional devices are achieved and compared to reference devices with standard SiO"2. Analysis of electron transport in these gate stacks is performed by specific MOSFET test structures that enable extraction of intrinsic inversion channel mobility. Attractive peak mobilities of 170cm^2/Vs have been found for GdSiO.

In this paper, epitaxial gadolinium oxide (Gd2O3) is reviewed as a potential high-K gate dielectric, both “as deposited” by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a “gentle” replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd2O3 gate dielectrics is explored by carefully controlling the annealing conditions.

The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd2O3) and silicon oxide (SiO2) on silicon substrates are compared after annealing at temperatures up to 1000°C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO2 layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT=0.95nm (lanthanum silicate) and EOT=0.6nm (epitaxial gadolinium oxide).

We report on leakage current mechanisms in epitaxial gadolinium oxide (Gd2O3) high-k gate dielectrics suitable for low standby power logic applications. The investigated p-type metal-oxide-semi con doctor capacitors are gated with complementary-metal-oxide-semiconductor-compatible fully silicided nickel silicide electrodes. The Gd2O3 thickness is 5.9 nm corresponding to a capacitance equivalent oxide thickness of 1.8 nm. Poole-Frenkel conduction is identified as the main leakage mechanism with the high-frequency permittivity describing the dielectric response on the carriers. A trap level of Phi(T) = 1.2 eV is extracted. The resulting band diagram strongly suggests hole conduction to be dominant over electron conduction. (c) 2008 The Electrochemical Society.

In this work, we present experimental results examining the energy distribution of the relatively high (>1×10^11 cm−2) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal–insulator–silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H2/N2 annealing following the gate stack formation, reveals a peak density (~2×10^12 cm−2 eV−1 to ~1×10^13 cm−2 eV−1) at 0.83–0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si(100). The characteristic peak in the interface state density (0.83–0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (Pbo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H2/N2) annealing over the temperature range 350–555°C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed.

We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd2O3 layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack (silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 °C anneal.