We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO 2 ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET Dit, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.

This work thoroughly investigates the external parasitic resistance in advanced FinFET technology. The optimization of the parasitic resistance is systematically examined in terms of 1) source/drain epi resistance, 2) contact resistance and 3) middle of line metal stud resistance. Various resistance reduction knobs have been experimentally explored in these three aspects and low contact resistivity of $1\times 10^{-9}$ and $7\times 10^{-10} \Omega\cdot \text{cm}^{2}$ have been demonstrated on transistor level for NFET and PFET. By combining all the parasitic resistance reduction strategies, more than 70% and 60% reductions [1] in external parasitic resistance have been realized on NFET and PFET, respectively.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.

In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10 −9 Q-cm 2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 μA/μm at Ioff = 10 nA/μm at VDD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.

IBM Microelectronics Division has recently developed and shipped its first advanced wiring density chip carriers which provide 50 /spl Omega/ impedance, via size down to 55 /spl mu/m diameter and 34 /spl mu/m line widths for high density I/O flip chip applications. The alumina chip carriers use thick film molybdenum features which can provide a wiring channel between 225 /spl mu/m pitch chip I/O connections for voltage and signal wiring. In some applications, the number of signal wiring layers can be reduced by a factor of two. The high density voltage and ground layers provide a low inductance path which minimizes voltage drop across the carrier, thereby optimizing chip power distribution. This characteristic is particularly important for high frequency operation. In many high chip I/O applications, the increased wiring density permits the use of up to 4 die shrinks, which can reduce overall module costs significantly. The increased wiring density is compatible with CPGA, CCGA, CBGA and CLGA form factors. This paper summarizes the key electrical attributes of the package and compares results for two design variations with advanced wiring chip carrier fabrication. It is shown that both design variations result in a 50 /spl Omega/ impedance package. Additionally, both designs result in improved power distribution with a reduction in signal switching noise. For a fully populated array design, 30% or more reduction in signal switching noise is obtained.