We introduce a fabrication scheme for strain-relaxed Ge, epitaxially grown on a Si-on-Nothing (SiON) template formed from macro-porous Si. The SiON template is fabricated on regular Si substrates using conventional lithography, dry-etching and annealing routines. The material properties of the virtual Ge substrate grown on this detachable template are identical to those obtained for Ge grown on bulk Si. Strain-relaxed, suspended, and detachable Ge-on-Nothing (GeON) was fabricated using a similar fabrication scheme except for the epitaxial growth of Ge on Si, which was performed before the patterning of the substrate. For GeON, the extracted excess carrier lifetime using time-resolved photoluminescence (32 ns) was > 4 times higher than the values measured for Ge grown on bulk Si with a similar thickness of the Ge layer. Both templates can be considered as starting material for layer transfer and 3D device stacking technologies provided that successful detachment from the parent substrate can be demonstrated.

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow . Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar I on -I off device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.

We report on p and n-type vertical gate-all-around (GAA) nanowire (NW) and nanosheet (NS) FETs which offer attractive opportunities for ultra-scaled circuits. An in-depth evaluation is presented on the impact of doping and key device dimensions to improve the performance, variability, noise and reliability behavior for junctionless (JL) vs. inversion-mode (IM) vertical FETs built with an RMG scheme. The latter enables a novel concept to introduce stress in VFETs for enhanced mobility with up to a19% higher I ON predicted. SiGe/Si pillars and self-aligned spacers offer a solution to gate vertical (mis)alignment towards the S/D. As MRAM selector, VNS FETs can allow substantial area reduction (64% for 2VNS per cell; 3nm node design rules) vs. finFET based cells, with smaller read/write energy consumption and latency times.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the ION performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of “reliability” anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

3D stacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature (T ≤ 525 ° C) in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiAl/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 degrees C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 degrees C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V-G = V-th + 0.6 V, 125 degrees C), even without the use of "reliability" anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

We are demonstrating for the first time epi-based monocrystalline silicon macaroni channel 3-D NAND devices. The highly controllable channel replacement process sequence leads to > 95% yield, with excellent uniformity and reproducibility, proving its potential for manufacturability. The electron mobility of the channel is improved by a factor 30 compared to the polycrystalline macaroni Si channel, together with a reduction of the off state leakage. Furthermore, this channel replacement fabrication process does not affect memory performance and reliability. The performance benefits of this channel replacement technique make it a potential candidate for fabricating future 3-D NAND devices.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channel-first schemes with improved process control, while tackling critical etch-layout dependences.

A 3D ferroelectric Al doped HfO 2 device for NAND applications was fabricated for the first time. The polysilicon (poly-Si) channel, whose diameter ranges from 60 to 200 nm, was highly doped for a better understanding of the ferroelectric properties. Electrical results confirmed the presence of the ferroelectric phase with a coercive voltage (2Vc) of 6 V extracted from the hysteresis loop. The drain anneal was found to have a significant impact on HfO 2 properties and needs to be reduced to preserve the ferroelectricity. Finally, reliability investigations showed an estimated time to failure of more than 10 years at 85 °C. This study lays the foundation for the fabrication of 3D ferroelectric field effect transistors (FeFET).

We are proposing a double gate junction-less device with a processing temperature compatible with state-of-the-art dense low k dielectric back-end of line copper process. The thermal stability of the back-end of line process was studied, showing no degradation for an anneal temperature up to 500°C 1h. Using wafer bonding, a crystalline silicon layer can be transferred onto a carrier wafer followed by top device processing at low temperature with a gate first approach as well as direct W contacts with Ti/TiN barrier layer. To avoid dopant activation using high temperature anneal (spike), junction-less devices are used, where the uniform channel dopant implantation and activation can be done prior to the layer transfer.

This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (V-min), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I OFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W NW ≤25nm, H NW ~22nm), with increased doping enabling ION improvement without I OFF penalty for W NW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V T mismatch performance shows higher A VT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d NW ≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low I OFF , I G , and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.

We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (V-min), and lower standby leakage values as compared to cells built with lateral GAA-NWFETs. Furthermore, vertical stacking of these devices also opens the path for SRAM 3D scaling, with a design presented here that can enable, with two levels of transistors in the vertical direction, to reduce by 39% the SRAM area per bit. The two vertically stacked VNWFETs are of the same doping type (n/n or p/p), and a lower complexity of implementation may be possible by taking advantage of the junctionless (JL) concept and its process simplicity, a topic also explored in this work.

We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL) GAA-NWFETs with excellent electrostatics and smaller IOFF values yield ring oscillators (RO) with substantially lower power dissipation and considerably longer BTI lifetime. Improved reliability is also obtained for extensionless vs. reference FETs with conventional junctions, at comparable device and circuit performance. In addition, a TiAl-based EWF-metal is introduced for the first time in a GAA configuration resulting in higher performing, low-VT, n-type GAA-NWFETs and single-MG 6T-SRAM cells. Noise results show no significant impact of device architecture on gate stack integrity and some benefit for JL and TiAl-based GAA-NWFETs.

For 28-nm embedded application, we have proposed a TaO x -based ReRAM with precise filament positioning and high thermal stability. The cell was realized using several newly-developed process technologies and cell structures: low-damage etching, cell side oxidation and encapsulated cell structure. As a result, we succeeded for the first time in forming a filament at the cell center. In addition, we confirmed the feasibility of 20-nm cell size. Excellent reliability was achieved in 2-Mbit 40-nm ReRAM: 100k cycles and 10 years' retention at 85°C was demonstrated.