This paper details the design and simulation-based evaluation of three distinct N-type-only low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) voltage reference circuits, tailored for the specific demands of flexible electronic systems. Addressing the inherent design challenges in TFT technology, these circuits employ a common strategy: generating a current with a negative temperature coefficient to compensate for proportional-to-absolute-temperature (PTAT) voltage characteristics. Comprehensive post-layout and statistical Monte Carlo simulation results highlight that the first of the proposed configurations achieves superior performance, exhibiting a temperature coefficient (TC) of 34.03 ppm/°C, a line sensitivity of 0.61 %/V, and a power supply rejection ratio (PSRR) of -42.34 dB. This study presents new circuit-level approaches for achieving reliable voltage references in flexible applications, thereby advancing the development of high-performance, flexible electronic systems.

This article describes a fully synthesizable digital-to-analog converter (DAC). It is important to develop an automated netlist generation and synthesizable design methodology for mixed-signal circuits. To fill in the scarcity of synthesizable DACs, we propose a multibit full-synthesizable current DAC using a shifting current mirror architecture with a multisegmented data weighted averaging (MSeDWA) mismatch correction algorithm. It provides robustness against process, voltage, and temperature (PVT) variations by means of a programmable bias generator, which suppresses the circuit variations by >2.7 & times;. The use of power-gating standard cells provides a flexible selection of current mirror types, thus achieving a widening of the voltage operation range. Moreover, stage separation and appropriate gain configuration ensure high linearity. With the MSeDWA technique, the total harmonic distortion (THD) is further improved by 7.7 dB. Operating between 14 to 56 MHz, the analog and digital circuits consume 8.64-56.64 & micro;W and 217-629 & micro;W, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.03 & micro;W/kHz while maintaining a maximum THD of 39.9 dB (1.01%).

The IoT landscape thrives on sensor application systems, enabling data-driven insights through diverse sensor technologies, ushering in a transformative era of data capture, transmission, and informed decision-making $[1-5]$. The nature of these signals can be classified into voltage, current, resistive, and capacitive (V/I/R/C) with various frequencies and dynamic ranges. Prior multi-modal integrated circuits [3–5] customized their analog front-end circuits based on the type of signals to achieve the best performance at the expense of design complexity, area, and power consumption. The reconfigurable signal acquisition circuit aims to use the least number of circuit components and configure itself to provide the correct signal conditioning interface, thereby addressing the aforementioned problems.

In digital integrated circuit (IC) design, the need for custom standard cells tailored to specific design constraints, such as power, area, and performance, is increasingly critical. This paper presents an approach that leverages Large Language Models (LLMs) to automate the translation and optimization of Boolean tables into custom pull-up networks, using established principles to generate complementary pull-down networks. The proposed methodology focuses on automated translation, optimization, and seamless integration into standard electronic design automation (EDA) workflows. By utilizing LLMs, this approach significantly reduces design time, enhances optimization, and minimizes human error. This makes it a powerful tool for improving the efficiency and effectiveness of custom standard cell design in digital logic circuits.

With the introduction of new process technology, the cost of developing standard cell libraries has escalated due to the need for multiple design iterations to optimize performance within given constraints. This challenge is compounded by the growing number of standard cells and process corners, and is further exacerbated by error-prone, manually-created netlists and test benches. In this work, we introduce the SCEval platform, where users can submit SPICE netlist files and receive corresponding evaluation results and charts post-simulation. Users can leverage our standardized SCEval platform to assess and enhance their standard cell circuits, which is integral to the DTCO process. Additionally, students new to standard cell circuit design can learn how to conduct standardized evaluations of standard cells through our platform.

This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over $2{\times }$ . These strengths underscore its significant impact and applicability in the domain of circuit design.

This paper investigates the use of fine-tuned ChatGPT, in Electronic Design Automation (EDA) for Design Rule Checking (DRC). As integrated circuits grow in complexity, so do the design rules, exacerbated by the diversity of EDA tools with unique DRC specifications. We introduce D2D-GPT, a unified tool leveraging ChatGPT’s language capabilities to translate DRC specifications across different EDA platforms. This research focuses on optimizing input datasets - native DRC rules - to improve ChatGPT’s translation accuracy and efficiency. Our objective is to streamline the EDA workflow, bridge gaps between various tools, and pave the way for more cohesive design processes in the semiconductor industry.

This paper presents a web-based LogicEdu education tool, designed to simplify Boolean logic expressions using genetic algorithms. It provides a user-friendly interface for students to input truth tables and obtain minimized logic expressions. We also explore its educational impact, particularly in enhancing understanding and engagement with Boolean algebra concepts through interactive learning. Preliminary results indicate that there is an improvement in students’ understanding.

The purpose of this article is to present two technical contributions geared toward the development of 2-D electrical impedance tomography (EIT) image reconstruction based on deep learning (DL) models, which aim to provide wearable EIT applications with the best balance between accuracy, memory consumption, and latency. First, an EIT-SYN dataset enumeration algorithm is proposed in order to address the scarcity of massive labeled datasets for training DL models. The circular contour dataset is used for training and benchmarking the DL model, and the thorax-like contour dataset is used to predict how well the model will perform in vivo. Second, a mixed precision asymmetric neural network model (EIT-MP) based on a convolutional auto-encoder (CAE) architecture is proposed, where the encoder network model is implemented on ASIC/FPGA hardware and performs data preprocessing and transfer to a computer while the decoder network model on the computer reconstructs the 2-D image. With the hardware-software co-optimization method, data can be compressed and encrypted for light and secure transmission. Experimental results demonstrate that the EIT-MP model reduces memory consumption by over 10.3x and achieves the best relative size coverage ratio (RCR) of 1.07 while maintaining a high image correlation coefficient (ICC) of 0.9220 and a short latency of 20.314 ms among state-of-the-art works. Therefore, our approach offers an appealing solution for image reconstruction in wearable EIT systems.

This paper presents a VCO-based ADC design for use in flexible electronics, specifically leveraging Low-Temperature Polysilicon Thin-Film Transistor (LTPS TFT) technology. The design achieves a resolution of 8.11 bits at a 20 MHz sampling rate with a bandwidth (BW) of 2.5kHz. A linearity compensation technique combining a resistive input stage with a frequency-dependent resistor (FDR)-based feedback loop significantly enhances the VCO linearity. Simulation results validate the design, exhibiting an R 2 value of 0.9999 for the VCO tuning curve, a Signal-to-Noise and Distortion Ratio (SNDR) of 50.57 dB, and a Spurious-Free Dynamic Range (SFDR) of 52.34 dB at a supply voltage of 10V. The proposed design also features the lowest Figure of Merit (FoM) (0.73 nJ/conversion-step) compared with the state-of-the-art.

This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.

This paper introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-up network (PUN) employs a Wilson current mirror to effectively reduce static current. The pull-down network (PDN) incorporates a diode-connected P-type transistor as a current limiter, further reducing static power consumption. An improved split-controlled inverter is introduced as the output driver to further minimize both static and short-circuit currents. The proposed level shifter can operate at a minimum VDDL of 100 mV at VDDH = 1.2 V and 1 MHz input frequency. Performance comparison with prior works reveals a significant performance improvement in terms of delay, power-delay product (PDP), and energy-delay product (EDP), with a delay of 4.79 ns, a PDP of 355 ns*nW, and an EDP of 326 fJ*ns when operating in a conversion range of 0.3 -1.2 V, making it a robust choice for energy-efficient ultra-low voltage level shifting applications.

Electrical Impedance Tomography (EIT) systems have shown great promise in many fields such as real-time wearable healthcare imaging, but their fixed number of electrodes and placement locations limit the system's flexibility and adaptability for further advancement. In this paper, we propose a flexible and reconfigurable EIT system (Flexi-EIT) based on digital active electrode (DAE) architecture to address these limitations. By integrating a reconfigurable number of up to 32 replaceable DAEs into the flexible printed circuit (FPC) based wearable electrode belt, we can enable rapid, reliable, and easy placement while maintaining high device flexibility and reliability. We also explore hardware-software co-optimization image reconstruction solutions to balance the size and accuracy of the model, the power consumption, and the real-time latency. Each DAE is designed using commercial chips and fabricated on a printed circuit board (PCB) measuring 13.1 mm × 24.4 mm and weighing 2 grams. In current excitation mode, it can provide programmable sinusoidal current signal output with frequencies up to 100 kHz and amplitudes up to 1 mA $_{p-p}$ that meets IEC 60601-1 standard. In voltage acquisition mode, it can pre-amplify, filter, and digitize the external response voltage signal, improving the robustness of the system while avoiding the need for subsequent analog signal processing circuits. Measured results on a mesh phantom demonstrate that the Flexi-EIT system can be easily configured with different numbers of DAEs and scan patterns to provide EIT measurement frames at 38 fps and real-time EIT images with at least 5 fps, showing the potential to be deployed in a variety of application scenarios and providing the optimal balance of system performance and hardware resource usage solutions.

This brief describes a high power efficiency, high linearity current driver for wearable electrical impedance tomography (EIT). It is extremely important to improve the power efficiency of the current driver circuit for wearable EIT applications because it consumes the majority of the power. As such, we propose a multi-stage shifting current mirror (S-CM) current-steering current driver circuit with customized dynamic element matching (DEM) techniques to suppress harmonic distortion (HD) to the greatest extent. Furthermore, the placement of switches in the current mirror circuit is optimized to reduce glitches during the switching phases. Operating between 14 MHz to 56 MHz, the power consumptions for the current mirror and the digital control logic are 21.6-141.6 $\mu $ W and 64.8-438 $\mu $ W, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.3 $\mu $ W/kHz while maintaining a total harmonic distortion (HD) of <–43 dB (0.7%).

Successive approximation register analog to digital converters (SAR ADCs) offer an attractive energy-efficient solution but its signal-to-noise-distortion-ratio (SNDR) is degraded due to its sensitivity to parasitic capacitance and capacitors' mismatch. In this article, we present an improved maximum likelihood estimation (MLE) algorithm, which offers a more robust estimator for statistical-based calibration technique that can be used across different resolutions of SAR ADC. The result has demonstrated that our proposed algorithm has further improved the SNDR up to 5.86 dB for a 12-20-bit SAR ADC with multisegmented digital-to-analog converter (DAC) compared to state-of-the-art algorithms.

Phantoms are used to evaluate, calibrate, and compare the performance of electrical impedance tomography (EIT) systems. This paper presents a dynamic thorax-like mesh phantom, which mimics the changes in electrical conductivity distribution within a human thorax at different time frames. Furthermore, element merging and contour smoothing, electrode placement techniques, and PCB design automation methods are proposed to simplify, optimize the mesh phantom, and reduce the hardware implementation cost. To verify the accuracy of the mesh phantom and its PCB, SPICE simulations and experimental testings are performed to obtain the conductance of the mesh phantom and reconstruct the images through the EIDORS software. These images achieve an image correlation coefficient (ICC) of 0.680 (model versus SPICE simulation) and 0.9098 (SPICE simulation versus measurement result), respectively. This demonstrates the validity of our proposed dynamic thorax-like mesh phantom.

Electrical Impedance Tomography (EIT) is a non-invasive and radiation-free clinical imaging technology, which is considered to be an effective substitute for CT and MRI. Assessing the performance of EIT requires a phantom for validation, calibration, and comparison. In this paper, we present a thorax-like mesh phantom that can effectively simulate the distribution of human thorax conductivity and optimize the mesh by reducing the number of resistors and exploring the optimal electrode placement. The proposed optimization methods are verified by Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and Electrical Impedance Tomography and Diffuse Optical Tomography Reconstruction Software (EIDORS) image reconstruction. Experimental results demonstrate that our proposed thorax-like mesh phantom gets a high image correlation coefficient (ICC) of 0.680 with only 313 resistors. Our proposed thorax-like mesh phantom can be used for EIT system validation and further promote the research of EIT system.