A platform for benchmarking tunnel field-effect transistors (TFETs) for analog applications is presented and used to compare selected TFETs to FinfET technology at the 14-nm node. This benchmarking is enabled by the development of a universal TFET SPICE model and a parameter extraction procedure based on data from physics-based device simulators. Analog figures of merit are computed versus current density to compare TFETs with CMOS for low-power analog applications to reveal promising directions for the system development. To illustrate the design space enabled by TFETs featuring sub-60-mV/decade subthreshold swing, two example circuits including a picopower common-source amplifier and an ultralow-voltage ring oscillator are demonstrated.

Formation of an electric double layer (EDL) is. a powerful approach for exploring the electronic properties of two-dimensional (2D) materials because of the ultrahigh capacitance and induced charge in the 2D materials. In this work, epitaxial graphene Hall bar devices are gated with an EDL using a 1 mu m thick solid polymer electrolyte, poly(ethylene oxide) and LiClO4. In addition to carrier density and mobility, ion dynamics associated with the formation and dissipation of the EDL are measured as a function of temperature over a gate bias range of +/- 2 V. The room temperature EDL formation time (similar to 1-100 s) is longer than the dissipation time (similar to 10 ms). The EDL dissipation is modeled by a stretched exponential decay, and the temperature-dependent dissipation times are described by the Vogel-Fulcher-Tammann equation, reflecting the coupling between polymer and ion mobility. At low temperatures, approaching the glass transition temperature of the electrolyte, the dissipation times of both cations and anions exceed several hours, and both p- and n-type EDLs can persist in the absence of a gate bias. The measured temperature-dependent relaxation times qualitatively agree with COMSOL multiphysics simulations of time dependent ion transport in the presence of an applied field.

A tunnel field-effect transistor (TFET)-based pixel circuit for well capacity adjustment that does not require subthreshold operation on the part of the reset transistor is presented. In CMOS, this subthreshold operation leads to temporal noise, distortion and fixed pattern noise, becoming a primary limiting performance factor. In the proposed circuit, the asymmetric conduction associated with TFETs is exploited. This property, arising from the inherent physical structure of the device, provides the selective well adjustments during photo-integration which are demanded for achieving high dynamic range. A GaN-based heterojunction TFET has been designed according to the specific requirements for this application.

The electrostatic gating of graphene field-effect transistors is demonstrated using a monolayer electrolyte. The electrolyte, cobalt crown ether phthalocyanine (CoCrPc) and LiClO4, is deposited as a monolayer on the graphene channel, essentially creating an additional two-dimensional layer on top of graphene. The crown ethers on the CoCrPc solvate lithium ions and the ion location is modulated by a backgate without requiring liquid solvent. Ions dope the channel by inducing image charges; the doping level (i.e., induced charge density) can be modulated by the backgate bias with the extent of the surface potential change being controlled by the magnitude and polarity of the backgate bias. With a crown ether to Li+ ratio of 5:1, programming tests for which the backgate is held at -VBG shift the Dirac point by ∼15 V, corresponding to a sheet carrier density on the order of 1012 cm-2. This charge carrier density agrees with the packing density of monolayer CoCrPc on graphene that would be expected with one Li+ for every five crown ethers (at the maximum possible Li+ concentration, 1013 cm-2 is predicted). The crown ethers provide two stable states for the Li+: one near the graphene channel (low-resistance state) and one ∼5 Å away from the channel (high-resistance state). Initial state retention measurements indicate that the two states can be maintained for at least 30 min (maximum time monitored), which is 106 times longer than polymer-based electrolytes at room temperature, with at least a 250 Ω μm difference between the channel resistance in the high- and low-resistance states.

A new type of flash memory will be presented based on the electrostatic doping of two-dimensional crystals using ions. The proposed device consists of two, 2D crystals separated by a 2D electrolyte through which the ions can pass. The top 2D crystal comprises the channel of a field-effect transistor (FET), while bottom 2D crystal is a backgate. When the ions are near the surface of the channel, they induce image charge in the channel and the device is the low resistance, or ON state. When the ions are pulled back to the backgate by an applied field, the device is in the high resistance or OFF state. The 2D electrolyte is cobalt crown ether phthalocyanine (CoCrPc) plus a salt, which can be deposited on the surface of 2D crystals simply by drop casting and annealing. The crown ethers solvate metal ions, and the ions can pass through the cavity of the crowns. Density functional theory (DFT) calculations show that the crown ethers present a small barrier to ion transport required for fast (nanosecond) switching, but the height of the barrier will be increased for long retention both by the image charge induced in the channel and by modulating the gate bias. The current-voltage characteristics of a simplified device architecture (monolayer CoCrPc:LiClO4 on graphene) will be presented. The graphene FET can be reconfigureably programmed by the 2D electrolyte, achieving sheet carrier densities of 4 x 1012 cm-2 at a low lithium concentration of 5 crown ethers to 1 Li+. Based on the geometric packing of the molecules, as determined by scanning tunneling microscopy, the doping density is predicted to increase to 5 x 1013 cm-2 at a crown ether to lithium ratio of 1:1. State retention measurements show that the two states can be retained for at least 30 minutes (maximum time measured to date) with a memory window of 10 uA. To increase the ON/OFF ratio and therefore the memory window, MoS2 FETs doped with the 2D electrolyte were also fabricated and similar bistable behavior is observed. This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA, and NSF grant #ECCS-GOALI-1408425. Figure 1

An analytical compact model for tunnel field-effect transistor (TFET) circuit simulation is extended by adding a gate tunnel current model, a charge-based capacitor model, and a noise model. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. To validate the gate current and charge models, technology computer-aided design (TCAD) simulations of a GaN/InN/GaN TFET are used. TCAD simulations show that the gate tunneling current depends on the gate-drain bias with a 100%/0% drain/source current partition. Terminal capacitances evaluated from the charge model agree well with simulations. The model is implemented in Verilog-A and the significance of gate current in the circuit design is illustrated in an amplifier design.

Low voltage transistors are being developed to achieve steep, less than 60 mV/decade, subthreshold swings at room temperature. This paper outlines progress, technical challenges, and applications for these devices.

The BaBi0.05Co0.8Nb0.15O3-delta (BBCN) oxide has been synthesized by the traditional solid-state reaction method and characterized for its application as new cathode material for intermediate-temperature solid oxide fuel cells (IT-SOFCs). The single phase BBCN having a cubic perovskite structure is obtained by Bi and Nb doping on the Co site in BaCoO3-delta. The electrical conductivities of the BBCN sample are 8.8-12.5 S cm(-1) in the temperature range 600-800 degrees C in air. The average thermal expansion coefficient (TEC) is 20.7 x 10(-6) K-1 in the range of 30-1000 degrees C in air. The activity of BBCN for oxygen reduction reaction (ORR) is tested by symmetrical cell and single fuel cell tests. The area specific resistance (ASR) of a BBCN cathode with LSGM electrolyte is 0.073 Omega cm(2) at 700 degrees C in air. A maximal power density of 610 mWcm(-2) is achieved at 800 degrees C. The BBCN cathode has shown a good electrochemical stability for 24 h short-term cell test. The experimental results indicate that BBCN can be a promising cathode candidate for IT-SOFCs. (C) 2014 Elsevier B.V. All rights reserved.

This extended abstract formulates a model of parallel performance called MMC. It gives the theoretical upper bound of parallel performance based on three factors: the processing capacity, the network capacity, and the memory capacity.

A simple analytic model based on the Kane–Sze formula is used to describe the current–voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model also captures the ambipolar current characteristic at negative gate–source bias and the negative differential resistance for negative drain–source biases. A simple empirical capacitance model is also included to enable circuit simulation. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.

As the understanding of tunnel field-effect transistors (TFET) advances, new approaches are emerging to lower off-currents, lower defect density in tunnel junctions, and to increase the highest current at which the subthreshold swing of 60 mV/decade (I 60 ) appears. III-N heterojunctions and transition-metal-dichalcogenide (TMD) materials are forcing some new thinking in junction design and doping.

15-Crown-5-ether-substituted cobalt(II) phthalocyanine (CoCrPc) is an atomically thin and flat-laying, electrically insulating molecule that can solvate ions; these properties are desirable for nanoelectronic devices. A simple, solution-phase deposition method is demonstrated to produce a monolayer of CoCrPc on highly ordered pyrolytic graphite (HOPG). A uniform and continuous CoCrPc layer is obtained on freshly cleaved HOPG by solution drop casting, followed by thermal annealing under ambient pressure in Ar in the temperature range of 150–210 °C. While the quality of the monolayer is independent of annealing time, the composition of the annealing atmosphere is critical; exposure to ambient air degrades the quality of the monolayer over the time scale of minutes. Using ultrahigh vacuum scanning tunneling microscopy, a highly ordered and flat CoCrPc layer with hexagonal symmetry and average spacing of 4.09 ± 0.2 nm is observed. The band gap of the CoCrPc, measured by scanning tunneling spectroscopy, is 1.3...

Emerging devices promise energy-efficient computing on a massively parallel scale, but due to the extremely high integration density the previously insignificant dissipation due to information erasure (destruction) becomes a prominent circuit design factor. The amount of heat generated by erasure depends on the degree of logical reversibility of the circuits and successful adiabatic charging. In this paper, we design an adiabatic arithmetic-logic unit to prototype the locally-connected Bennett-clocked circuit design approach. The results indicate one or two orders-of-magnitude energy savings in this physical circuit implementations vs. standard static CMOS. Previous work on computer arithmetic suggests that common hardware implementations erase much more information than would be required by a theoretical minimal mapping of the addition operation. A Bennett-clocked approach can reach the theoretical minimum number of bit erasures in the binary addition, though simulations show that a transistor technology has energy loss due to parasitic components that can exceed the information loss heat. In this paper, we describe the relationship between adiabatic and logically reversible circuits, and predict the potential of the arithmetic implementations based on quantum-dot cellular automata, which enable the full benefits of reversible, locally connected circuits to be realized.

A simple analytic model based on the Kane-Sze formula is proposed to describe the current-voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.

Progress in the development of tunnel field-effect transistors (TFETs) is updated. Selected experimental demonstrations and simulations of sub-60-mV/decade TFETs are compared. A universal SPICE model is discussed which allows the unique attributes of the TFET to be represented across material systems and gate geometries to enable circuit design, with the intent of better informing the device development.

Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1-10 nA/μm. A common approach to TFET characterization is proposed to facilitate future comparisons.

Doping technologies are needed for the development of tunnel field-effect transistors based on graphene and other single-layer two-dimensional materials. Here we utilize Li + and ClO 4 − ions in polyethylene oxide (PEO) to enable dynamic and reconfigurable doping of graphene under electric field control. Ions are drifted across the PEO to the graphene where they induce electron or hole conductivity. Use of PEO:LiClO 4 for ion-doping of carbon nanotubes [1], graphene [2, 3] and MoS 2 [4] have all incorporated the ion conductor and field plate above the transistor channel. This requires a dry process because the developers used in photolithography attack and contaminate PEO. This further restricts the field plate formation process to shadow evaporation or to macroscopic contacts formed by probes. Here we report on a new dry transfer process which allows the transistor to be placed on top of the PEO and the doping to be field-controlled by the substrate back gate. In this paper we show the transfer process and characteristics of the ion motion and conductivity modulation under field-control. The dry transfer process is illustrated in Fig. 1. To create the top portion of the device, source and drain contacts are patterned onto wide area graphene formed by chemical vapor deposition. Polyisobutylene (PIB) and a PDMS stamp are then applied as handling layers (Fig. 1b). The Cu substrate is then etched in ammonium persulfate (APS) and the top portion is joined to the bottom (Fig. 1e). We have fabricated devices with both Au and graphene backgates, and initial tests were performed with an Au backgate, patterned into stripes to minimize leakage current through the electrolyte (Fig. 2). Doping in the graphene channel is controlled by the backgate voltage ( V bg ). The conductivity, monitored by the drain current, ( I d ), is varied by a factor of four by sweeping V bg at 0.5 V/s from −10 to 10 V (Fig. 3). The shift of the current minima (Dirac points) from zero are a direct measure of the ion doping of the graphene channel. To characterize the retention of electrostatic doping, a 5 V backgate pulse is applied for 1 second and removed for 10 seconds while monitoring the drain current (Fig. 4). The current decreases by ~10% as the ions are polarized and then released. Acknowledgements: This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. [1] C. Lu et al. Nano Lett. 4 , pp. 623–627 (2004) [2] A. Das et al ., Nat. Nanotech , 3 , pp. 201-215 (2008) [3] D. Efetov and P. Kim, Phys. Rev. Lett., 105 , pp. 256805 (2010) [4] M. Lin, et al. , J. Phys. D , 45 , 345102 (2012).

Overcoming the IC power challenge requires signal energy recovery, which can be achieved utilizing adiabatic charging principles and logically reversible computing in the circuit design. This paper demonstrates the energy-efficiency of a Bennett-clocked adiabatic CMOS multiplier via a simulation model. The design is analyzed on the logic gate level to determine an estimate for the number of irreversible bit erasures occurring in a combinatorial implementation, showing considerable potential for minimizing the logical information loss.