A technique has been developed for characterizing the disorder present in thin films through the measurement of their low temperature internal friction. The technique utilizes a substrate, in the form of a double paddle oscillator etched from a high purity silicon wafer, onto which the thin film of interest can be deposited. The oscillator possesses an internal friction of 3 × 10−8 at 4 K which is reproducible to within 1% upon thermally cycling to room temperature. This extremely small substrate internal friction coupled with the excellent reproducibility permits measurements of the internal friction of very thin amorphous films, with a 2 tun silica film producing a change in the internal friction of 4 × 10−9. By performing low temperature internal friction measurements on thin silica films with thicknesses ranging from 2 nm to 1000 nm, we have investigated the role of interacting defects in determining the universal nature of the anomalous low temperature thermal and elastic properties of amorphous solids. We have found no evidence for strong interactions between these tunneling defects. Other applications of the oscillator include monitoring of the crystallization of amorphous films through changes in the low temperature internal friction, internal friction measurements and vapor pressure measurements of quenched condensed rare gas solids and amorphous water ice, and internal friction studies of amorphous solids which can only be produced in thin film form.

The lattice vibrations of crystalline solids are generally described by traveling elastic waves. However, the vibrations of fullerene solids are expected to be quite different from typical crystalline solids because of the large molecular mass. In fact, based on measurements of thermal conductivity and specific heat, it appears that the vibrations of compacted fullerene solids are best described as locahzed. Only below a few Kelvin has evidence for elastic waves been found in these solids where they exist along with the locahzed tunneling states that are characteristic of amorphous solids. In order to verify the existence of these tunneling defects, the low temperature internal friction of thin fullerene films deposited on a silicon substrate has been measured. Fullerene films were prepared under a variety of conditions with substrate temperatures ranging from 300 K to 500 K. Film grain sizes were characterized using atomic force microscopy, as well as, scanning tunneling microscopy. Grain sizes were found to range between 100 nm and 400 nm. We find that while locahzed tunneling defects appear to be present in these films, they do not appear to be intrinsic to the fullerene solid. Instead, the tunneling states may be the result of residual disorder that is present in the grain boundaries of the solids.

We report on the development of a hafnium zirconate (HfZrO4) alloy gate dielectric for advanced gate stack applications. The HfZrO4 and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors. The HfZrO4 material properties were examined and compared with those of HfO2 by a wide variety of analytical methods. The dielectric properties, device performance, and reliability of HfZrO4 were investigated by fabricating HfZrO4/tantalum carbide (TaxCy) metal-oxide-semiconductor field effect transistor. The HfZrO4 dielectric film has smaller band gap, smaller and more uniform grains, less charge traps, and more uniform film quality than HfO2. The HfZrO4 dielectric films exhibited good thermal stability with silicon. Compared to HfO2, the HfZrO4 gate dielectric showed lower capacitance equivalent thickness value, higher transconductance, less charge trapping, higher drive current, lower threshold voltage (Vt), reduced capacitance-voltage (C-V) hysteresis, lower interface state density, superior wafer level thickness uniformity, and longer positive bias temperature instability lifetime. Incorporation of zirconium dioxide (ZrO2) into HfO2 enhances the dielectric constant (k) of the resulting HfZrO4 which is associated with structural phase transformation from mainly monoclinic to tetragonal. The tetragonal phase increases the k value of HfZrO4 dielectric to a large value as predicted. The improved device characteristics are attributed to less oxygen vacancy in the fine grained microstructure of HfZrO4 films.

The intent of this research is to understand the role of interface chemistry on the effective work function and device characteristics of metal gate electrodes on hafnium dioxide (HfO2) gate dielectrics in metal oxide semiconductor field effect transistors. Since multiple factors, including crystal structure, preferred orientation, chemical composition, interface bonding, and reactions or interdiffusions, impact the effective work function, solid-solution carbonitrides of tantalum (TaCxN1−x) have been studied in an attempt to isolate the role of interface chemistry on the effective work function. Tantalum carbonitride films have been carefully deposited with similar Ta∕(C+N) ratios to understand how the substitution of N for C on the octahedral interstice in a face-centered-cubic tantalum lattice impacts device performance. Results indicate that the effective work function and device threshold voltage are reduced when the less electronegative carbon atom is substituted for the more electronegative nitrogen atom. This result is in qualitative agreement with the known relationship between metal electronegativity and effective work function and demonstrates the important role that sublattice elements in binary metal compounds have on the effective work function of the gate electrode.

Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.

The empirical relationship between electronegativity and effective work function is applied to a diverse set of multielement electrode materials on hafnium dioxide (HfO2) gate dielectrics. To accommodate the multi-element nature of metal gate electrodes the group electronegativity of the metal was calculated from the geometric mean of electronegativity with respect to the volume stoichiometry of the constituent elements. Results show a reasonable linear fit that provides guidance for the selection of metal gate electrodes on HfO2. The group electronegativity concept is also extended to work function engineering via dielectric capping materials. The electronegativity trends provide insight into the relative charge neutrality levels of candidate dielectric capping materials and their subsequent impact on the metal effective work function.

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

The impact of Zr addition on microstructure of HfO2 after high temperature processing was investigated using Rutherford backscattering, x-ray diffraction (XRD), transmission electron microscopy, and atomic force microscopy (AFM). The ZrO2 content in the films was varied from ∼25% to 75%. XRD analysis shows that adding >50% ZrO2 leads to partial stabilization of tetragonal phase of the HfxZr1−xO2 alloy. AFM images revealed smaller grains with Zr addition. Conducting AFM showed more uniform and tighter tunneling current distribution in HfxZr1−xO2 compared to HfO2. Constant capacitance-voltage stressing performed on HfO2 and HfxZr1−xO2 metal-oxide-semiconductor capacitors indicated reduced charge trapping with Zr addition.

A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs. E-field universal curve and those with similar bulk layer lie on the same PBTI vs. E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI

This paper compares the performance and inter-die variability of doped and undoped channel multiple-gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrow-width planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar devices, conversions to undoped channel FinFETs is necessary. Furthermore, good short-channel control has to be maintained since undoped channel devices exhibit increase sensitivity to Tbody relative to doped channel FinFETs due to enhanced fully-depleted channel electrostatics

We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45mn low power (LP) CMOS technology. Inversion To,. (T-inv)values of 16 angstrom/18 angstrom (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm(2) and enable self-heated drive currents of 850/325 mu A/mu m at InA/mu m off-state leakage and V-dd=1V (900/340 mu A/mu m non-self-heated). Additionally, the NMOS drive current of 1550uA/[mu m (1650 mu A/mu m non-self-heated) at an I-off= 100nA/mu m and V-dd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures. (1).

Atomic layer deposited HfO2 films void and exhibit poor electrical characteristics when annealed at high temperature unless a TiN capping layer is used. The TiN is removed prior to characterization of the dielectric. The authors find that capped HfO2 films annealed at 1000°C by rapid thermal process are smooth and void-free. The microstructure of HfO2 is modified from fully monoclinic to a mixed monoclinic and tetragonal phase when the capping layer is used. Conducting atomic force microscopy performed on these films shows fewer areas with high leakage current. Mo∕HfO2 capacitors show improved CV characteristics and lower leakage current density.

Thin film characteristics of HfO2-TiO2 mixed oxides and nanolaminates formed by atomic layer deposition were studied using transmission electron microscopy (TEM), atomic force microscopy, X-ray reflectometry, and metal oxide semiconductor capacitors. The role of HfO2 underlayer and the impact of the location of TiO2 in HfO2-TiO2 gate dielectrics were also investigated. Some differences in grain-size distribution were observed between mixed oxides and nanolaminates. In mixed oxide films, the grains became smaller and clustered together to form elongated structures as TiO2 is added. For nanolaminates, the grains became smaller than HfO2 but they did not form elongated structures. Cross-sectional TEM showed that as-deposited HfO2-TiO2 films were amorphous with a thinner interfacial layer than that of HfO2. After annealing, films became rougher, with an increase in interfacial layer thickness. A minimum of 20 cycles of HfO2 (similar to 10 A) was needed as an underlayer to obtain well-behaved electrical characteristics. Capacitance-voltage stressing performed on these films showed improved charge trapping behavior for mixed oxide and nanolaminate structures.