Power wall has become one of the main bottlenecks of future VLSI designs. A recently proposed junctionless twin-gate Vertical Slit Field Effect Transistor (VeSFET) is a low power and thermal friendly device, with highly regular layout, and two-side accessibility. These properties are critical for advanced 2D/3D technologies. SRAMs are fundamental blocks of VLSI systems, which are usually used for technology evaluation. This paper provides a VeSFET SRAM performance assessment modeled by CACTI, a cache modeling tool. The results show that VeSFET SRAM design is speed competitive to CMOS SRAM with about 40% of dynamic read energy consumption and 35% of total power consumption for read access rate 100MHz.

Thermal management becomes a huge challenge for modern IC designers, especially when chips go 3-D. Vertical slit field-effect transistor (VeSFET) technology provides an alternative thermal-friendly design choice. VeSFET-based chips not only have a much lower power density but also a better vertical thermal conductivity than their CMOS counterparts. For a VeSFET chip with ten stacked dies, the temperature increase is only 30% of that for CMOS-based chip. Assuming the same scaling trend for CMOS and VeSFET, VeSFET 3-D chips can postpone the appearance of dark silicon by three technology nodes compared with CMOS implementations. For VeSFET-based designs, different topologies of transistor arrays may result in different thermal behaviors. We perform thermal characterization of two-transistor array topologies.

In this note, the concept of Vertical Slit Transistor Based Integrated Circuits (VeSTICs) is introduced and its feasibility discussed. VeSTICs paradigm has been conceived in response to the rapidly growing complexity/cost of the traditional bulk-CMOS-based approach and to challenges posed by the nano-scale era. This paradigm is based on strictly regular layouts. The central element of the proposed vision is a new junctionless Vertical Slit Field Effect Transistor (JL VeSFET) with twin independent gates. It is expected that VeSTICs will enable much denser, much easier to design, test and manufacture ICs, as well as, will be 3Dextendable and OPC-free.

In this paper, we demonstrate that standard cell design methodology can be applied to design vertical slit field effect transistor (VeSFET)-based ASICs with modern CMOS EDA tools. We study a family of VeSFET canvases-chain canvases that improve performance and power consumption of circuits mapped to them compared to circuits implemented with VeSFET canvases composed of isolated transistors. We compare the designs implemented with a commercial low power CMOS library and corresponding VeSFET libraries. VeSFET-based designs demonstrate significant power reduction as compared to the CMOS-based designs at the same performance.

Thermal management constitutes a huge challenge for CMOS or FinFET-based circuits, especially when chips go 3D. VeSFET provides an alternative thermal-friendly design choice. Device simulations show that temperature increase due to self-heating is very small for VeSFET transistors. At chip level, VeSFET-based 2-D and 3-D chips not only have much lower power density, but also have better vertical thermal conductivity than their CMOS counterparts. Peak temperature of a 10-die VeSFET chip is only 18K higher than ambient temperature. Temperature increase of a working 10-die 3-D VeSFET chip is 70% less than that of a similar CMOS configuration.

Vertical Slit Field Effect Transistors (VeSFETs) are novel twin-gate and junction-less devices with nearly ideal sub-threshold swing and manufactured using SOI infrastructure. In this paper, we analyze VeSFETs as potential components of ultra-low power circuits. We compare circuits built with VeSFETs, FinFETs, and bulk-MOSFETs, all in 65nm technology node. Our experiments demonstrate that VeSFET has the smallest intrinsic capacitance and the lowest minimum energy among the studied devices. The Tied-Gate (TG) VeSFET-based circuit operating at the minimum energy point achieves a lower energy and a higher frequency than its Independent-Gate (IG) VeSFET-based counterpart. IG VeSFET achieves lower energy for circuits working at extremely low and relatively wide frequency range.

The silicon implementation of junction-less Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS processes is presented. The twin poly-Si gates on the side walls of the vertical slit are defined using damascene process making them self-aligned and free from lithography restrictions on tall features. The NMOS transistors fabricated on 42 nm wide and 117 nm tall slit showed excellent electrical characteristics: ION = 20µA, ION/IOFF ratio = 10 9 , SS = 62mV/dec, DIBL = 13mV/V. The second gate could be used for providing better electrostatic control, threshold voltage tuning, or additional functionality.

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high I ON /I OFF ratio (>; 10 6 ). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

This work follows the recent work on fabrication-based feasibility assessment of N-Channel Vertical Slit Field Effect Transistor (VeSFET) (1). For the first time, we demonstrate AND/OR functionality in the single device by varying the slit width. The fabricated n-channel VeSFETs with AND and OR functionalities exhibit good electrical performance with low off current of 10 -13 A and high ION/IOFF ratio of ~10 7 .

Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.

In this presentation feasibility of Vertical Slit Transistor Based Integrated Circuits (VeSTICs) is evaluated. VeSTICs paradigm has been conceived as a response to the rapidly growing complexity of the traditional CMOS-based approach to challenges posed by the nano-scale era. This paradigm has been constructed using notion of a strict layout regularity imposed on VeSTIC layouts. The central element of the proposed vision is new junction-less Vertical Slit Field Effect Transistor (VeSFET) with twin independent gates. It is expected that VeSTICs will enable much denser, much easier to design, test and manufacure ICs, as well as, will be 3D-extendable and OPC-free. (More exhaustive description of this paradigm one can find at: http://vestics.org). This talk reviews all of the above VeSTICs characteristics. The focus of the talk, however, is on first silicon results (just obtained with simple SOI-like process), extremely low power and dependency between actual achievable transistor density and layout design rules. These characteristics are compared to a variety of traditional CMOS-based paradigms using the same infrastructure.

This paper introduces a new device architecture, which can be shared by a variety of different types of transistors including a new 3D junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs) [2,3]. This paper discusses the basic idea of vertical slit device architecture, the physics of VeSFETs, their key electrical properties in comparison with trigate FinFETs, and shows experimental characteristics of fabricated devices.

Sub-wavelength lithography uses light waves that have a longer wavelength than the feature size that is being printed. Image distortions are an inevitable consequence of this situation, even after resolution enhancement techniques have been applied. This paper studies in detail how the image distortion in a fabricated IC can impact test and critical-area yield loss. Particularly, lithography simulation is performed on the desired pattern to predict the printed (distorted) pattern. The impact on critical-area yield loss is studied using both the desired pattern and the printed pattern. Similarly, the impact on test is studied using inductive fault analysis on both the desired pattern and the printed pattern. Even under the assumption of the best process conditions, experiment results indicate that the difference in misdirected test effort can be as large as 8.0% and the difference in the critical-area yield calculations is about 3.4% for a large design. The more accurate analysis requires a runtime increase of 5X on average.

The highly complex design process for 2.5-D VLSI requires automatic Electronic Design Automation tools. In this chapter we propose a layout design framework for 2.5-D ICs. The building blocks include floorplanning, placement, and routing tools, which are capable of packing a logic circuit into a stacked space.

4 design case studies using the 2.5-D integration scheme are presented in this chapter. The first 3 designs, a crossbar circuit, a Rambus DRAM, and a reconfigurable data-path (PipeRench), are re-designed by exploiting fine-grain inter-chip interconnects. The 4th design study involves a 3-D stacked CPU/memory system. The above design cases studies validate the potential of the 2.5-D integration paradigm from a performance point of view.

In this paper, we study circuits implemented using high-density arrays composed of vertical slit field effect transistors. This layout style could dramatically increase transistor density and, therefore, reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks, pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing.

In this chapter we elaborate on the need for new 3-dimensional VLSI paradigms by extrapolating the trend of technology development. On such a basis, we will propose our target 2.5-D integration scheme, and then explain its advantages. The fabrication, testing, and design technologies to enable the 2.5-D scheme are explained. Finally we are going to introduce the objectives and organization of this book.