In this work, we demonstrate a back-end-of-line (BEOL)-compatible seed-iteration-epitaxy (SIE) technique, achieving high-quality Si crystallization with a grain size of 1.83 μm and an integrity factor of 0.9. The SIE technique consists of two sequential steps: (1) grain-filter (GF)-based seed preparation to form high-quality poly-Si seeds and (2) seed-assisted crystallization, where liquid phase epitaxy (LPE)-like growth occurs using the underlying seeds as templates. At the device level, by utilizing the SIE approach, excellent electrical performance is achieved for NMOS, showing ON-OFF current ratio (ION/IOFF) of 2.1 × 107, subthreshold swing (SS) of 82.8 mV/dec, and field-effect mobility (μFE) of 605 cm²/V·s. This approach provides a promising pathway for integrating high-mobility channel materials with potential relevance to future three-dimensional integration and memory applications.

In this article, the drain-induced barrier lowering (DIBL) is taken as a smart indicator for the lateral positioning of hot-carrier-induced trap distribution. A distinct asymmetry in DIBL due to hot-carrier degradation (HCD) is observed upon source/drain swapping. The ratio of DIBL degradation at normal source/drain configuration and reverse mode is defined as the P parameter, which is less than 1 to indicate the trap generation at the source side and larger than 1 for the drain side. With $P$ parameter extraction in nanoscale n-FinFET, it is found that the oxide traps initially dominate and shift from the source to the drain, and then, interface traps take over and shift from the drain toward the source, when ${V}_{\text {ds}}$ increases from 1.3 to 3.5V with ${V}_{\text {gs}}$ of 1.4 and 1.8 V under HCD stress. This observed shift highlights the crucial role of impact ionization (I/I)-generated secondary carriers in shaping the lateral damage profile. Based on these experimental findings, a physical model is proposed and conclusively verified through TCAD simulations, offering a predictive framework for reliability assessment.

As integrated circuit technology node continues to advance, SiNx film deposition in evolving three-dimensional structures with higher integration density and large aspect ratios faces challenges from conformity and tunable film properties. This paper investigates the impact of incident energy and substrate temperature on the microstructural properties and surface morphology of SiNx thin film growth by plasma enhanced chemical vapor deposition process, on nanoscale silicon substrate with different aspect ratios. We conduct both experiments and molecular dynamics simulation to investigate the deposition performance of SiNx thin films. The results indicate that SiNx film microstructure will be more disordered as the temperature and energy increase. The density of SiNx film shows a significant dependence on the substrate temperature, when the temperature increases from 353 K to 673 K, density increases from 2.43 g/cm3 to 2.71 g/cm3. However, the kinetic energy increase does not result in a significant change in film density. We also observe that the substrate temperature exhibits little impact while gas kinetic energy significantly increases the deposition rate. Finally, we characterize the conformity of deposition on nanoscale structures by calculating step coverage. With larger open width, higher temperature and higher gas kinetic energy, the film conformity improves. These results may enable development of efficient manner for process optimization and film property tuning in advanced manufacturing.

Plasma-enhanced chemical vapor deposition (PECVD) is a critical technique in integrated circuit manufacturing. As semiconductor devices continue to scale down in advanced technology nodes, the details of PECVD processes are difficult to be captured by traditional Technology Computer Aided Design (TCAD) approaches. In this study, we present a Monte Carlo approach to predict the profile evolution of Si3N4 thin film deposition by PECVD at feature scale. By employing a new transport algorithm for reactive species in vacuum, our method achieves an atomic-level modeling of deposition profile evolution within acceptable computational time. Experimental validation demonstrates that this model achieves a mean prediction errors below 10 % for the deposition of trenches with different aspect ratios.

In this article, to optimize the performance of silicon-on-insulator (SOI) stacked Si nanosheet (NS) gate-all-around field-effect transistor (GAAFET) with long source/drain (S/D) regions, special process techniques of Ni(Pt)Si silicide-first and Load-Si thinning are successfully integrated in the experimental devices. Because of the introduced silicide-first process, the transistor performance merits of ON-current (I-ON) and transconductance (G(m)) are also increased by 34.19% and 80.55% for the reduction of 68.66% in the S/D parasitic resistance. Meanwhile, compared to the Bulk-Si GAAFET, the gate-induced drain leakage (GIDL) current of the SOI GAAFET is also decreased by more than one order of magnitude. However, the subthreshold characteristics of SOI GAAFETs exhibit a rapid degradation as the gate length (L-g) scaling, which is mainly due to the effect of parasitic channel in the remaining Load-Si layer. To optimize the leakage and subthreshold characteristics, the electrical impacts of Load-Si thickness (TLoad-Si) are thoroughly investigated by the experiment and TCAD simulation. The experimental SOI GAAFET fabricated by thinning Load-Si to 19 nm has obtained better subthreshold characteristics, improved normalized I-ON, and caused an obvious decrease of OFF-current (I-OFF) at L-g=30 nm. Meanwhile, the simulation results further show that the SOI GAAFET with shorter L-g needs to continuously decrease TLoad-Si to meet the requirements of a fully depleted channel and low I-OFF.

A new type of vertical sandwich gate-all around tunneling field-effect-transistors (TFETs), called VSATFETs, was demonstrated firstly with a CMOS-compatible process. The VSATFETs with self-aligned high-κ metal gates (HKMG) and abrupt doping tunneling junctions were fabricated with the epitaxial of p+−Si/i-SiGe/n+−Si sandwich structure and an isotropic quasi-atomic layer-etch (qALE) process. VSATFETs have the advantage of excellent control of channel size, because its gate-length is mainly determined by the thickness of SiGe film grown by epitaxy, and the diameter of the nanowires (NWs)/thickness of nanosheets (NSs) is determined by the qALE etching of SiGe selective to Si. A NW VSATFET with a diameter of 18 nm was fabricated and exhibits excellent characteristics: SS min = 61.64 mV dec −1 , I on = 2.25 × 10 −7 A u −1 m −1 (@V gs −V t = 0.45 V, V d = 0.65 V), I on /I off = 1.81 × 10 6 , DIBL = 7.58 mV. The effect of interface traps on the device performance was analyzed by the calibrated model. It is found that the device performance can be improved by decreasing the thickness/diameter of NS/NW TFET.

Based on the bulk-Si substrate, the CMOS tree-like FETs including the FishboneFETs with bottom SiGe nano-fin and the TreeFETs without bottom SiGe nano-fin were both designed and experimentally fabricated. The growth of bottom SiGe layer with different Ge fraction following by an accurately selective etching is developed for realizing SiGe nano-fins between Si nanosheets (NSs). The results show that the ${I}_{\text {on}}/{I}_{\text {off}}$ ratio (over ${1}\times {10} ^{{5}}{)}$ and the short channel effects (SCEs) of TreeFETs are effectively optimized, and the effective channel width ( ${W}_{\text {eff}}{)}$ is increased for FishboneFETs at the same footprint. Due to the hole conduction advantage of SiGe nano-fin, the on-current ( ${I}_{\text {on}}{)}$ of p-type TreeFETs can be higher than that of n-type TreeFETs at ${V}_{\text {OV}}=\vert V_{\text {gs}}$ - ${V}_{\text {th}}\vert =0.5$ V. Meanwhile, the surface scattering of SiGe nano-fin also affects the effective field-effect mobility. As the gate length ( ${L}_{\text {g}}$ ) scaling, both p-type tree-like FETs exhibit more obvious SCEs than n-type devices, which is maybe the reason of a lower hole barrier occurring by the valence band offset ( $\Delta {E}_{\text {v}}{)}$ obtained in the strained SiGe nano-fin. The results provided one meaningful guide for tree-like FETs optimizing future GAAFET process and CMOS circuits.

Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern pitch and stack layer thickness on lateral etch results have been studied by simulation.

Advanced silicon photonic technologies enable integrated optical sensing and communication (IOSAC) in real time for the emerging application requirements of simultaneous sensing and communication for next-generation networks. Here, we propose and demonstrate the IOSAC system on the silicon nitride (SiN) photonics platform. The IOSAC devices based on microring resonators are capable of monitoring the variation of analytes, transmitting the information to the terminal along with the modulated optical signal in real-time, and replacing bulk optics in high-precision and high-speed applications. By directly integrating SiN ring resonators with optical communication networks, simultaneous sensing and optical communication are demonstrated by an optical signal transmission experimental system using especially filtering amplified spontaneous emission spectra. The refractive index (RI) sensing ring with a sensitivity of 172 nm/RIU, a figure of merit (FOM) of 1220, and a detection limit (DL) of 8.2*10-6 RIU is demonstrated. Simultaneously, the 1.25 Gbps optical on-off-keying (OOK) signal is transmitted at the concentration of different NaCl solutions, which indicates the bit-error-ratio (BER) decreases with the increase in concentration. The novel IOSAC technology shows the potential to realize high-performance simultaneous biosensing and communication in real time and further accelerate the development of IoT and 6G networks.

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 μA/μm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 μA/μm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 μW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.

This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dimensional (3D) integration schemes with alternative materials and device architectures will pave paths for future technology evolution. Finally, it could be concluded that Moore’s law will undoubtedly continue in the next 15 years.

The CA1, an important subregion of the hippocampus, is anatomically and functionally heterogeneous in the dorsal and ventral hippocampus. Here, to dissect the distinctions between the dorsal (dCA1) and ventral CA1 (vCA1) in anatomical connections, we systematically analyzed the direct inputs to dCA1 and vCA1 projection neurons (PNs) with the rabies virus-mediated retrograde trans-monosynaptic tracing system in Thy1-Cre mice. Our mapping results revealed that the input proportions and distributions of dCA1 and vCA1 PNs varied significantly. Inside the hippocampal region, dCA1 and vCA1 PNs shared the same upstream brain regions, but with distinctive distribution patterns along the rostrocaudal axis. The intrahippocampal inputs to the dCA1 and vCA1 exhibited opposite trends, decreasing and increasing gradually along the dorsoventral axis, respectively. For extrahippocampal inputs, dCA1 and vCA1 shared some monosynaptic projections from certain regions such as pallidum, striatum, hypothalamus, and thalamus. However, vCA1, not dCA1, received innervations from the subregions of olfactory areas and amygdala nuclei. Characterization of the direct input networks of dCA1 and vCA1 PNs may provide a structural basis to understand the differential functions of dCA1 and vCA1.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

This article focuses on how to improve the negative capacitance (NC) properties of NMOSFET in the gate-last process flow. The impacts of the HfZrO ferroelectric film thickness, metal gates with different work functions, stress of filled metal gate, the thickness of seed layer underneath HfZrO etc. on NC effect are investigated, and the corresponding possible mechanisms are discussed. These techniques have been successfully applied to the fabrication of NC-NMOSFETs with physical thickness 1.5-nm HfZrO, and underneath with 1.0-nm ZrO2 seed layer. The NC-NMOSFETs with much improved subthreshold swing (SS) of 38.6 mV/decade and nearly hysteresis free are developed with a gate length of 900 nm, and the SS is over 40 mV/decade smaller than that of the control-2 NMOSFETs with 2.5-nm HfO2 gate dielectric only.

Understanding the connecting structure of brain network is the basis to reveal the principle of the brain function and elucidate the mechanism of brain diseases. Trans-synaptic tracing with neurotropic viruses has become one of the most effective technologies to dissect the neural circuits. Although the retrograde trans-synaptic tracing for analyzing the input neural networks with recombinant rabies and pseudorabies virus has been broadly applied in neuroscience, viral tools for analyzing the output neural networks are still lacking. The recombinant vesicular stomatitis virus (VSV) has been used for the mapping of synaptic outputs. However, several drawbacks, including high neurotoxicity and rapid lethality in experimental animals, hinder its application in long-term studies of the structure and function of neural networks. To overcome these limitations, we generated a recombinant VSV with replication-related N gene mutation, VSV-NR7A, and examined its cytotoxicity and efficiency of trans-synaptic spreading. We found that by comparison with the wild-type tracer of VSV, the NR7A mutation endowed the virus lower rate of propagation and cytotoxicity in vitro, as well as significantly reduced neural inflammatory responses in vivo and much longer animal survival when it was injected into the nucleus of the mice brain. Besides, the spreading of the attenuated VSV was delayed when injected into the VTA. Importantly, with the reduced toxicity and extended animal survival, the number of brain regions that was trans-synaptically labeled by the mutant VSV was more than that of the wild-type VSV. These results indicated that the VSV-NR7A, could be a promising anterograde tracer that enables researchers to explore more downstream connections of a given brain region, and observe the anatomical structure and the function of the downstream circuits over a longer time window. Our work could provide an improved tool for structural and functional studies of neurocircuit.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

We experimentally investigate the effect of post-deposition annealing on the charge distribution of a metal-oxide-semiconductor capacitor with a TiN/HfO 2 /SiO 2 /Si gate structure. We decoupled interfacial charges at the SiO 2 /Si and HfO 2 /SiO 2 interfaces; bulk charges in HfO 2 ; and the dipole formation at the HfO 2 /SiO 2 interface. The interfacial charges at the HfO 2 /SiO 2 interface decreased and the dipole increased after H 2 or N 2 annealing. Oxygen dangling bonds are the physical origin of the charges at the HfO 2 /SiO 2 interface. The interfacial charges at the SiO 2 /Si interface and the bulk charges in HfO 2 are almost unchanged.

Duplications of MECP2-containing genomic segments led to severe autistic symptoms in male. Transgenic mice overexpressing the human MECP2 gene exhibit autistic-like behaviors. Neural circuits underlying social defects in MECP2 transgenic (MECP2-TG) mice remain unknown. To observe neural activity of MECP2-TG mice in vivo, we performed calcium imaging by implantation of microendoscope in the hippocampal CA1 regions of MECP2-TG and wild type (WT) mice. We identified neurons whose activities were tightly associated with social interaction, which activity patterns were compromised in MECP2-TG mice. Strikingly, we rescued the social-related neural activity in CA1 and social defects in MECP2-TG mice by deleting the human MECP2 transgene using the CRISPR/Cas9 method during adulthood. Our data points to the neural circuitry responsible for social interactions and provides potential therapeutic targets for autism in adulthood.

Innate defensive responses are essential for animal survival and are conserved across species. The ventral tegmental area (VTA) plays important roles in learned appetitive and aversive behaviors, but whether it plays a role in mediating or modulating innate defensive responses is currently unknown. We report that VTAGABA+ neurons respond to a looming stimulus. Inhibition of VTAGABA+ neurons reduced looming-evoked defensive flight behavior, and photoactivation of these neurons resulted in defense-like flight behavior. Using viral tracing and electrophysiological recordings, we show that VTAGABA+ neurons receive direct excitatory inputs from the superior colliculus (SC). Furthermore, we show that glutamatergic SC-VTA projections synapse onto VTAGABA+ neurons that project to the central nucleus of the amygdala (CeA) and that the CeA is involved in mediating the defensive behavior. Our findings demonstrate that aerial threat-related visual information is relayed to VTAGABA+ neurons mediating innate behavioral responses, suggesting a more general role of the VTA.

ABSTRACTMapping the detailed cell-type-specific input networks and neuronal projectomes are essential to understand brain function in normal and pathological states. However, several properties of current tracing systems, including labeling sensitivity, trans-synaptic efficiencies, reproducibility among different individuals and different Cre-driver animals, still remained unsatisfactory. Here, we developed MAP-ENVIVIDERS, a recombinase system-dependent vector mixing-based strategy for highly efficient neurocircuit tracing. MAP-ENVIVIDERS enhanced tracing efficiency of input networks across the whole brain, with over 10-fold improvement in diverse previously poor-labeled input brain regions and particularly, up to 70-fold enhancement in brainstem compared with the current standard rabies-virus-mediated systems. MAP-ENVIVIDERS was over 10-fold more sensitive for cell-type-specific labeling than previous strategies, enabling us to capture individual cell-type-specific neurons with extremely complex axonal branches and presynaptic axonal boutons, both about one order of magnitude than previously reported and considered. MAP-ENVIVIDERS provides powerful tools for deconstructing novel input/output circuitry towards functional studies and disorders-related mechanisms.