The memory wall due to data movement is a major challenge that limits performance and energy efficiency in bitwise-operation-intensive applications. To address this issue, this paper proposes a global merged reference-based magnetic random-access memory (MRAM) logic-in-memory structure. The proposed structure generates operation-specific reference resistances by controlling the effective parallelism of the reference bitlines (Ref-BLs) while maintaining the initial reference-cell configuration, thereby supporting memory read and two-input AND/OR operations without rewriting the reference cells or using dedicated AND/OR logic blocks. A read-disturbance-free scheme is also applied to protect the frequently accessed reference cells. A 32-kb test chip fabricated in a 28-nm FD-SOI process achieved sensing yields of 100%, 98.63%, and 99.73% and normalized energies per bit of 0.97×, 0.54×, and 0.49× relative to conventional MRAM for memory read, OR, and AND operations, respectively. Full-system evaluations achieved speedups of 2.23×–2.50× and 3.14×–4.97×, with normalized dynamic energy consumption of 0.39×–0.44× and 0.23×–0.30×, for bitmap-index queries and bitmap-based breadth-first search, respectively.
This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct down-conversion mixing, which avoids a dedicated LO generator, coupler, or standalone detector path. Implemented in a 65-nm CMOS process and operated from a 1-V supply, the prototype consumes a total of 400 μW, including 375 μW for the LNA and 25 μW for the PD. Measurements show an S21 of 14.5 dB, S11 of −12.9 dB, noise figure of 4.5 dB, IIP3 of −7.5 dBm, and input-referred 1-dB compression point (P1dB) of −17.5 dBm at 2.8 GHz. The embedded PD provides a monotonic output response over more than 20 dB input range while occupying only 0.012 mm2. The proposed architecture enables compact RF power sensing for adaptive low-power receivers, including interference-resilient front-ends with frequency-selective limiters.
A resistor-less 7-bit source-series-termination (SST) DAC-based transmitter (TX) with an 8-tap feedforward equalizer (FFE) is presented. Three different resistor-less SST segments (SSTSs) are employed to achieve low capacitance, compact area, and scaling friendliness. To reduce the output jitter of 4:1 multiplexer due to the inter-symbol-interference (ISI), the dual-feedback equalizer (DFEQ) is proposed. This TX is fabricated in 28-nm CMOS and has a maximum output swing of 1.1 Vppd. For the 112-Gb/s PAM-4 and 168-Gb/s PAM-8 data, the calculated energy efficiency is 1.59 pJ/b and 1.06 pJ/b, respectively.
We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor terminated front-end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the 4-lane link operates at 64 Gb/s/pin with a bit error rate less than 10-12 while consuming only 0.25 pJ/b (0.2 pJ/b at 50 Gb/s) from a 1-V supply, and achieves bandwidth density greater than 28 Tb/s/mm2.
This letter presents a broadband, high-OMA GaN-based 1-to-N VCSEL driver implemented in 150-nm GaN HEMT process for parallel and wireless optical transmitter frontends. It further compares split-node and conventional VCSEL-driving topologies and analyzes the bandwidth scaling and inter-VCSEL timing skew of series- and parallel-connected VCSEL arrays. Leveraging the high voltage-handling and driving capability of GaN, the proposed architecture supports series-connected VCSEL arrays, thereby reducing the effective capacitive loading while increasing the aggregate optical output. With a four-series VCSEL array, the driver demonstrates 40-Gb/s NRZ transmission with approximately 8-mW total OMA and 38-Gb/s PAM-4 operation. Preliminary FSO measurements further show that increasing the number of series-connected VCSELs improves the received optical signal strength and extends the transmission distance, validating the proposed driver for wireless optical links.
We present the first ASIC demonstration of SQIsign, an isogeny-based NIST-candidate post-quantum digital signature scheme. Our optimized Montgomery modular multiplier circuit design enables 2× speedup and energy savings, while efficient memory organization provides 31% area savings. We implement SQIsign-1D-Uncompressed signature verification in a small form factor with low power consumption suitable for embedded applications. Our hardware achieves an order-of-magnitude improvement in performance and energy-efficiency compared to state-of-the-art assembly-optimized software. Our finite field arithmetic implementation can be extended to other isogeny-based cryptography algorithms, thereby facilitating future quantum-safe migration.
This letter presents a 42-Gb/s differential PAM-3 transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard deviation of the M-level offset by 40% in 1,000-run Monte Carlo simulations. Fabricated in 28-nm CMOS, the prototype occupies 0.015 mm² and consumes 66.3 mW at 42 Gb/s, achieving 1.58 pJ/b. Measurements verify M-level offset compensation under mismatch emulation and improved eye openings with a 3-tap feed-forward equalizer (FFE).
This paper presents a low-power 10Mbps squaring-first ultra-wideband (UWB) receiver using frequency hopping code-division multiple-access (FH-CDMA) and two-tone OOK modulation for wireless personal area networks (WPAN). The two-tone receiver architecture preserves IF filtering, improves resilience to narrowband interference, and saves power by eliminating the RF local oscillator. FH is applied to both two-tone spacing and center frequency, where spacing-FH enables multiple-access communication, while center-FH distributes signal energy across the UWB spectrum and improves NBI tolerance. Implemented in 65nm CMOS, the receiver achieves -71.4dBm sensitivity at 10Mbps while consuming 987μW, demonstrating improved tolerance to a 6GHz blocker and 1dB sensitivity degradation under two-user reception.
This paper proposes an offset-canceling discharge-based sensing circuit (OCDC) for STT-MRAM. The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage (VTH) mismatch cancellation, resolving the structural incompatibility between conventional OC schemes and MRL. A diode-connection-based self-biasing mechanism further eliminates the need for an external clamp voltage generator, providing robustness against PVT variations. A 30,720-bit test chip fabricated in a 28-nm FD-SOI process demonstrates that at VDD = 0.8 V and tsen = 2 ns, the OCDC reduces the fail bit count from 2,007 to 0 for Read 0 and from 3,957 to 2 for Read 1 compared to the conventional sensing circuit. The robustness of the proposed circuit is further validated through Monte Carlo simulations over a temperature range of −45 °C to 90 °C and an MTJ resistance variation ranging from 6% to 15%.
This work presents a minimal nonvolatile flip-flop (NVFF) hybrid architecture and an NV static contention-free differential FF (nvSCDFF) cell that reduce the overhead associated with replicated NV circuitry in conventional in-situ NVFFs while enabling low-power. By using only one NVFF per column and compact SCDFF-based volatile FFs, the design removes per-cell write drivers and sense amplifiers, reducing area, power, and energy. A symmetric self-referenced sensing achieves the required 4σ restore yield without assist circuitry. Monte Carlo simulations and a 28-nm test chip demonstrate robust restore operation and low voltage functionality.
Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses dynamic offset between coarse and fine decisions. Additionally, a sampling-phase pull-up drives the comparator input pair into cutoff, shaping the input capacitance and extending the linear input range. Implemented in a 12-nm FinFET process, the proposed comparator is integrated into an 11-bit, 4-GS/s, 8-way time-interleaved SAR ADC. The prototype occupies 0.12 mm² and consumes 20 mW from a 1.2-V supply. Measurement results show a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 53.5 dB and a spurious-free dynamic range (SFDR) of 70.1 dBc, corresponding to a Walden figure-of-merit (FoM) of 12.9 fJ/conversion-step.
This letter presents a 12-bit, 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for a fast-response characteristic, a high-gain residue amplifier (RA) featuring a two-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The preamplifier incorporates a polarity-aligned common-mode feedback (CMFB) technique that minimizes Miller capacitance while implementing a noninverting feedback loop, thereby eliminating the conventional auxiliary inverting amplifier. Furthermore, a hardware-efficient asynchronous SAR logic based on an improved 6-transistor true single-phase clocking (TSPC)-DFF is developed to reduce power and shorten the logic path. The prototype ADC achieves 64.5-dB SNDR and 81-dB SFDR at Nyquist input, while consuming 3.7 mW from a 1.2-V supply.
This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin bandwidth without increasing the data rate. The SBD transceiver was demonstrated using four-phase hybrid timing alignment and dual equalization. The bidirectional signals are aligned on both sides through CH reach optimization at the target frequency. This simplifies the bidirectional signals on both sides and reduces echo effects. The hybrid scheme using four-phase clocking mitigates RX margin reduction due to TX replica mismatch. In addition, a dual equalization scheme is proposed to compensate for the bidirectional ISI of the SBD signal. The prototype transceiver is implemented using RDL fan-out wafer-level package (FOWLP) and fabricated in a 1b-nm DRAM process with 70-& micro;m bump pitch, such as HBM4. The transceiver supports the SBD operation up to 18.4 Gb/s/pin on 6-mm traces, similar in length to the HBM4 system. The transceiver achieves the highest perpin bandwidth compared to previous works.
This letter presents a compact, multiband reflection-type phase shifter (RTPS) implemented in 65-nm CMOS that overcomes the narrowband limitations of conventional passive loads. The proposed design utilizes an inductive-load modulation. By injecting a secondary signal to actively manipulate the magnetic flux, the equivalent inductance is boosted to enable operation across three distinct millimeter-wave (mmWave) bands (27-29 GHz, 32-34 GHz, and 36-38 GHz) without any area penalty. Measurements confirm a continuous 180 degrees phase tuning range with a flat insertion loss (IL) profile (10 +/- 1 dB) across all operating frequencies. The RTPS demonstrates state-of-the-art precision, achieving a worst case rms phase/gain error of <0.38 degrees and <0.12 dB. Systemlevel validation using a 200-MSym/s 256-QAM signal further verifies robust signal integrity, achieving an error vector magnitude (EVM) of -34.48 dB.
This article presents an experimental characterization of a novel 6-bit parallel-to-serial data converter integrated with a Manchester encoder. The system comprises an on-chip digital logic block that generates six mutually nonoverlapping control signals (phi 0-5) and three 120 degrees phase-shifted clock signals to drive the switching transistors in the serializer and the Manchester encoder (MCE), respectively. This system was fabricated on a 27-pm-thick flexible polyimide substrate using an NMOS-only, single-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) technology. From measurements, the system has shown a reliable functionality up to a clock frequency of 2 MHz with a power dissipation of 750 & micro;W at a supply voltage (V-DD) of 2 V. This system's active area is 6.16 mm(2). To validate the proposed system functionality in biomedical applications of practical importance, it was deployed at the output of a 6-bit charge-sharing analog-to-digital converter (CS-ADC), which was also fabricated on the same flexible foil under the same conditions. Here, the digital output of the CS-ADC has been serialized and encoded with the proposed system, where an ECG signal is an input to the SAR-ADC. The encoded outputs from the serializer were further postprocessed in MATLAB to recover the original signal, validating the system's functionality. This work serves as a proof-of-concept for a fully integrated, compact, and low-power data interface suitable for flexible health-monitoring systems in wearable applications.
