In this work, we explored an efficient automatic layout routing algorithm for connecting the power and ground pins in analog integrated circuits. A rectilinear minimal spanning tree (RMST) algorithm for two sets of pins is developed, in which minimal spanning tree is used to form the initial connections between pins. The obstacle-avoiding maze routing algorithm is used to break and reconnect the power and ground nets to avoid any short circuit. The genetic algorithm (GA) is further introduced to optimize the total connection wirelength. We also expanding the wire width to avoid electromigration and IR-drop.
The periodic stacked film etching is a key enabler of 3D device manufacturing. This work demonstrates a silicon oxide/tungsten/titanium nitride periodic stack etching in one etching step. Because of the chemical reaction mechanism differences for various materials, a wave-like sidewall is always observed after one step etching. Sub-100nm holes on single and periodic stacks are etched with Cl2/NF3/C4F6/Ar gases. By tailoring the gas ratio and bias power, passivation distribution and ion bombardment strength are optimized and a smooth sidewall with an excellent vertical profile is achieved.
Previously in 2020, the author proposed a new unified theory regarding the image force dielectric constant for Schottky emission leakage current in high-k dielectric. In this paper, the author will try to point out that this theory can be applied to ferroelectric hafnium zirconium oxide (HfZrO) capacitor structures.
As for engineering verification, such as three-temperature test, corner test and wafer factory transfer, some experimental processing has been done on the chip, resulting in some parameters of the chip being slightly shifted compared with normal bin1 chip. As a result, some marginal fail would occur if tested by normal FT (Final Test) program. But these chips are good at EVB (Evaluation Board) verification. In this case, if need a test program to cover these chips, test engineers need to increase power voltage or slow frequency for the corresponding test item. In SMT7 (Smartest7) program, it may need to modify hundreds of level or timing spec (specification) values and generate a test program with a new, loosen spec value, which would take at least one day. This paper introduces a solution that can provide a simple excel format tool for input modification, a flexible operator configuration to deal with spec value and develop a new test program with the click of a few buttons. It’s highly integrated, comprehensively improves program development efficiency and is easy to use.
Spiking Neural Network (SNN) mimics the biologically inspired neural network that benefits for the computing with low power and high parallelism. In this paper, a scalable and configurable low-power mixed signal neuromorphic accelerator is proposed for the SNN application. It consists of 64 neurons, 64 synapses, 64×64 Static Random-Access Memory (SRAM) array, 64×64 Content Addressable Memory (CAM) array and a number of digital asynchronous routers. 15×64 neurons are fully connected by proposed scalable architecture. The proposed neuromorphic accelerator is designed in 65 nm CMOS process dissipating 4.8 mW at 100 MHz of clock frequency from a 1.2 V power supply.
